MB20 core memory
From Computer History Wiki
The MB20 was a core main memory system for the later PDP-10s, principally the mid-period KL10. An MB20 contained up to four memory controllers, each with up to four 32KW storage modules, for a maximum of 512KW; parity is provided to protect the memory contents. The access time is 1.04 µseconds, and the cycle time is 1.92 µseconds (both for the first word in a 4-word block, using four-way interleaving).
It connected to the so-called internal memory bus, the S-Bus, which performs memory transfers in blocks of 4 words, so that 4 words can be read in any cycle. The KL10 contains a pair of S-Busses; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1.
