Talk:MB20 core memory

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Interleaving

Memory interleaving:

https://images.slideplayer.com/25/8010523/slides/slide_11.jpg

Basically you start access on the first word, then while you read the first word, the memory controller starts access on the second word, and while you read the second word, the memory controller starts access on the third word,

Now, depending on burst length, like 8 words, you can restart access on the first word again, while you are reading the fourth word, and start the cycle over again, until you reach the length of the burst length.

The iPX 420 did bit interleaving. the 8088 did byte interleaving, ( 8bit processor 1 word interleaving. ) the 8086 also did byte interleaving, the 286 did word interleaving, two bytes at a time, the 386 did word interleaving, 4 bytes at a time, but it had to start on a 4 word boundry for the first read.

ForOldHack (talk) 10:55, 21 March 2019‎ ‎ (CET)

Err, I do actually know about interleaving (worked on machines that used it, back in the day); that "still trying to understand interleaving" really meant 'still trying to understand the interleaving on the MB20'.
BTW, what you've described isn't really interleaving (in the classical sense of that term); not sure of the exact term for the above, it's kind of like pipelined multi-word block reads. Interleaving is when you have two (for 2-way interleaving) separate memory controllers (each with an associated block of storage), and reads to location N and N+1 each go to different controllers. This is useful for core memory, since it's destructive readout (i.e. on read, the data has to be written back), so the cycle time is considerably longer than the access time. (And now that I look, the interleaving article doesn't include that bit about why the cycle time is longer for core, I'll have to add it.) Jnc (talk) 15:15, 21 March 2019 (CET)

Mid-period

What is a "mid-period KL10"? What period is that, and what are the associate hardware characteristics? Larsbrinkhoff (talk) 05:57, 5 July 2019 (CEST)

Hmmm... trying to reconstruct what I was thinking when I wrote that!
I guess that at a hardware system level, there are two main KL10 variants, those with internal and external memory. But for the CPUs, there are a number of subtle variations (not all of which I remember off the top of my head); e.g. I seem to recall there are 'Model B' KL10's, which sort of implies there must have been an 'A' - and I forget the differences between them. Then there's extended addressing, and also ISTR there were different amounts of microcode.
None of which is laid out in the KL10 article, we should fix that.
I guess by 'mid-period KL10' I was referring more to a temporal thing, rather than a particular hardware configuration; I meant early internal memory machines (since later ones all want to DRAM). Jnc (talk) 15:35, 5 July 2019 (CEST)
So I've done a certain amount of work improving the KL10 article. Turns out the other differences between the model A and B (the ucode size was already mentioned) is that the A had only a single DTE PDP-11 interface (which explains why MC's second PDP-11 was on a DL10), and no RH20 support (apparently no C Bus). I still need to find out and add more details about multi-section support, though.
Also, I have this bit set that the MB20 mounted in the main CPU cabinet (hence the 'internal' and 'external' terms); I need to find documentation about that. Jnc (talk) 18:16, 5 July 2019 (CEST)
Thanks! For what it's worth, some of my recent additions was triggered by me backporting MC's RH10 & RP04 code to work on the KA10 ITS machines. I also looked into adding RH20 support and eventually run on a KL model B, but that's considerably more work. Larsbrinkhoff (talk) 19:08, 5 July 2019 (CEST)
So the MB20 was indeed mounted in the CPU bays, but that's not what 'internal' means, rather it refers to use of the SBus.
Speaking of which, the SBus was subtly different in later machines (MF20, etc) and was renamed the XBus. Something else that's different between early and late KLs, and which needs to be investigated and written up. It may have come in at the same time as section support (which required a CPU replacement, including the backplane). Jnc (talk) 21:27, 5 July 2019 (CEST)