UNIBUS Experimental Ethernet interface
A UNIBUS Experimental Ethernet interface was produced in small numbers by Xerox PARC, to allow PDP-11's to be connected to Experimental Ethernets. It was a full-duplex device, which used DMA to transfer packets directly to and from main memory.
The network interface was a hex board which plugged into an UNIBUS SPC slot; a flat cable led from a Berg connector on the card to a bulkhead connecter, from where a standard Ethernet cable led to the transceiver.
The network address (8 bits on the Experimental Ethernet) was set by a DIP switch on the card. Also, the hardware did not fill in the source address in the packet header, the device driver had to do that.
One minor oddity (by today's standards) was that the back-off after a collision was implemented by software, in the device driver. A third interrupt vector was used when a collision occurred, not the normal output vector.
Contents
- 1 Device registers
- 1.1 760020: Output Word Count Register
- 1.2 760022: Output Bus Address Register
- 1.3 760024: Output Control and Status Register
- 1.4 760026: Output Start Delay Register
- 1.5 760030: Input Word Count Register
- 1.6 760032: Input Bus Address Register
- 1.7 760034: Input Control and Status Register
- 1.8 760036: Interface Network Address Register
- 2 External links
Device registers
Register | Address |
---|---|
Output Word Count Register | 760020 |
Output Bus Address Register | 760022 |
Output Control and Status Register | 760024 |
Output Start Delay Register | 760026 |
Input Word Count Register | 760030 |
Input Bus Address Register | 760032 |
Input Control and Status Register | 760034 |
Interface Network Address Register | 760036 |
760020: Output Word Count Register
Unused | WC9 <---> WC0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
The two's complement of the number of words to transfer.
760022: Output Bus Address Register
BA15 <---> BA01 | Unused | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
16-bit main memory addresses restricted buffers to the low 64KB of memory.
760024: Output Control and Status Register
Error | Unused | Done | Int Enb | Unused | Enable | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Error was set by either a collision, or data was not available from the bus in time.
760026: Output Start Delay Register
Unused | Delay | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
760030: Input Word Count Register
Unused | WC9 <---> WC0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Although the documentation avers that this is a two's complement number, a device driver source code indicates that in fact it was a one's complement counter.
The count needed to include the CRC word in the packet (otherwise on a maximum-sized packet an error would be indicated), but this was not actually transferred to memory.
760032: Input Bus Address Register
BA15 <---> BA01 | Unused | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
760034: Input Control and Status Register
Error | Unused | Done | Int Enb | Unused | Prom | Enable | |||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Error was set on a CRC error, buffer overflow, or when the bus did not take a word in time.
The 'promiscuous' bit caused all packets to be received, not just ones addressed to this interface.
760036: Interface Network Address Register
Unused | NA7 <---> NA0 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |