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• Multi-port memory
  ...e physically separately connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[channel]]s, [[Direct Memory Access|DMA]] [[device controller ...ntention ever happens (since each port has its own private copy of all the data). If more than one port can write, however, contention may arise in the wri
  1 KB (192 words) - 16:36, 15 December 2018
• UNIVAC I
  ...ords each (to reduce access times over fewer, larger lines). The [[Central Processing Unit|CPU]] operated in digit-serial mode (i.e. a digit at a time), to match ...nly [[input/output]] devices were [[magnetic tape]] units, the 'UNISERVO'. Data could be transferred to and from tape with off-line [[peripheral]]s which a
  2 KB (319 words) - 01:12, 12 July 2023
• Punched card
  ...[[secondary storage|data storage]] in the early period of computer usage. Data was stored in them by the presence, or absence, of holes punched in pre-det ...became a world-wide colossus before World War II on its dominance of card processing.
  2 KB (279 words) - 16:45, 5 December 2023
• KB11-A CPU
  The '''KB11-A''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/45]]. The optional [[FP11-B * M8100 Data and Address Paths
  3 KB (395 words) - 21:08, 2 July 2023
• KB11-D CPU
  The '''KB11-D''' [[Central Processing Unit|CPU]] is the later [[Central Processing Unit|CPU]] for the [[PDP-11/45]]; it differed from the earlier [[KB11-A CPU * M8100 Data and Address Paths
  2 KB (307 words) - 12:32, 11 October 2022
• Multi-processor
  A '''multi-processor''' is a system with more than one [[Central Processing Unit|CPU]]. There are a tremendous range of designs, from 'tightly-coupled' * MIMD - 'multiple instruction streams, multiple data sets'
  1 KB (204 words) - 03:37, 28 November 2023
• KE11-E Extended Instruction Set
  ...hex]] board, the M7238, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]], and also connects up to the basic CPU's [[microco ...which produces an additional 24 bits width of microcode (to control the [[data path]]s and [[register]]s on the M7238), but also provides 44 bits of micro
  2 KB (304 words) - 02:33, 12 October 2022
• FP11-F Floating-Point Processor
  ...card (the '''M7093'''), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]]. The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP
  961 bytes (149 words) - 02:20, 13 October 2022
• KD11-Z CPU
  The '''KD11-Z CPU''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/44]]; the terminal letter code 'Z' was a tip to ...devices were attached to a semi-separate [[UNIBUS]] (it and the EUB shared data lines, but not address lines); [[Direct Memory Access|DMA]] devices could g
  4 KB (668 words) - 15:59, 6 February 2024
• KB11-B CPU
  The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on * M8130 Data Paths
  3 KB (456 words) - 21:08, 2 July 2023
• Bit-mapped display
  ...'s main [[bus]], with the display memory directly visible to the [[Central Processing Unit|CPU]] as [[main memory]]. Due to the intimate relationship with the re | 1971 || [[Data Disc]] || [[Stanford Artificial Intelligence Laboratory|Stanford AI Lab]] |
  3 KB (448 words) - 12:21, 27 February 2024
• National Semiconductor NS405 and NS455 Terminal Management Processor
  ...] provide complete [[video terminal]] functionality, including a [[Central Processing Unit|CPU]] which can use either internal or external [[read-only memory|ROM ...itsavers.trailing-edge.com/pdf/zentec/Zentec_ADM3_Retrofit/NS405.pdf NS405 data sheet]
  1 KB (164 words) - 04:42, 27 February 2023
• Memory interleaving
  ...erently has a much longer cycle time since it has destructive readout; the data has to be written back before a read cycle can complete.)
  2 KB (349 words) - 23:12, 29 July 2023
• Expression
  ...is then used in some way - perhaps saved in [[main memory]] or a [[Central Processing Unit|CPU]] [[register]] for use later in the [[program]].
  436 bytes (70 words) - 19:38, 14 December 2018
• OMNIBUS
  ...rammed I/O]], in which the [[Central Processing Unit|CPU]] reads or writes data to the [[device controller]]; * '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access|DMA]].
  2 KB (325 words) - 04:52, 19 September 2021
• PDP-8/L
  ...] in the [[PDP-8 family|PDP-8]] line; it apparently had the same [[Central Processing Unit|CPU]] as the -8/I. ...differed from the MC-8/I of the PDP-8/I in that the Instruction Field and Data Field [[register]]s were only one bit wide, not three bits as in the MC-8/I
  2 KB (298 words) - 14:11, 14 July 2023
• Intel 80486
  ...or]]s, the 4th generation in that line. It is basically the same [[Central Processing Unit|CPU]] as the 386, but includes an 8K byte [[cache]], and optionally (i ...he two used in the 386, speeding it up considerably. Its [[main memory]] [[data bus]] is 32 [[bit]]s wide, the same as the 386.`
  1 KB (219 words) - 13:26, 3 November 2018
• FPP8/A Floating Point Processor
  ...|CPU]], but used [[Direct Memory Access|DMA]] for its [[instruction]]s and data.
  680 bytes (114 words) - 22:25, 22 November 2019
• Intel Pentium
  Externally, it is functionally the same [[Central Processing Unit|CPU]] as the 486, but includes a number of internal improvements to in ...[[cache]]s, one each for [[object code|code]] and data, so that [[loop]]s processing large [[array]]s will not empty the cache.
  1 KB (183 words) - 13:46, 3 November 2018
• Co-processor
  ...s in tandem with the main CPU, under its direction, to perform some of the processing functions of the system.
  528 bytes (79 words) - 16:25, 15 December 2018

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