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• Register renaming
  ...''' is a technique used in the implementation of [[superscalar]] [[Central Processing Unit|processors]], particularly in those using [[out-of-order execution]], ...sters, more than can be named in the instructions - use of these keeps the data in the CPU, where it is quickly accessible. Register renaming is however ne
  1 KB (191 words) - 16:05, 15 December 2018
• UNIX V6 dump analysis
  ...omething happens it can't recover from; or after [[halt]]ing the [[Central Processing Unit|CPU]]. ...nd the per-process kernel [[stack]]), as well as the user's data (both the data area, and the user stack) in a single contiguous block in main memory, and
  4 KB (719 words) - 12:07, 2 July 2022
• KD11-K CPU
  The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management * Data Path (M7874)
  4 KB (536 words) - 12:34, 11 October 2022
• FP11-E Floating Point Processor
  which mounted in slots 8-11 of the [[Central Processing Unit|CPU]]'s [[backplane]]. The main CPU can detect the presence of the FP1 ..., it connected directly to the CPU and is controlled by it; unidirectional data buses are provided to move information (including instructions) from the CP
  1 KB (229 words) - 02:19, 13 October 2022
• MD10 core memory
  ...stem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  1 KB (231 words) - 13:54, 2 August 2023
• MA10 core memory
  ...ystem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  1 KB (165 words) - 13:53, 2 August 2023
• MB10 core memory
  ...stem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  881 bytes (134 words) - 13:53, 2 August 2023
• ME10 core memory
  ...ystem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  1 KB (181 words) - 13:55, 2 August 2023
• MF10 core memory
  ...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  2 KB (271 words) - 12:37, 5 November 2023
• MG10 core memory
  ...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  2 KB (342 words) - 12:33, 5 November 2023
• MH10 core memory
  ...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  3 KB (407 words) - 12:40, 5 November 2023
• MF20 MOS memory
  ...ovided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be
  2 KB (278 words) - 15:50, 24 October 2022
• MG20 MOS memory
  <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[ ...G20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could
  2 KB (355 words) - 15:49, 24 October 2022
• RH20 MASSBUS controller
  ...ory of the system, to allow it to use [[Direct Memory Access|DMA]] to move data directly from devices to main memory, without needing CPU intervention.
  2 KB (294 words) - 12:59, 12 November 2023
• DLV11-F asynchronous serial line interface
  ...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen; it can also
  3 KB (469 words) - 01:19, 17 February 2023
• KE11-A Extended Arithmetic Element
  ...hift operations. As a UNIBUS peripheral, not integrated into the [[Central Processing Unit|CPU]], it was also usable with other models, e.g. the [[PDP-11/05]] an ...20-777336. The operation to be performed is selected by the register which data is written to. Registers which hold results are readable, but many of the o
  5 KB (680 words) - 21:17, 2 July 2023
• Able UNIVERTER
  ...y the low-level details differ. (E.g. the UNIBUS carries [[address]]es and data on separate [[conductor|lines]], whereas the QBUS carries them both on a se ...s that the [[bus grant|bus arbiter]], and the interrupt-fielding [[Central Processing Unit|processor]], be on the QBUS. The UNIVERTER does not have to be at the
  2 KB (251 words) - 18:32, 5 December 2022
• Bus Arbitration on the Unibus and QBUS
  ...(sometimes multiple processors) and peripheral devices together and allows data transfers between the various components. As a general rule, one and only o ...asserts BBSY and becomes the bus master. The requesting device now can run data transfer bus cycles. When it's done, the requesting device negates SACK and
  21 KB (3,685 words) - 04:35, 28 November 2023
• DM11-BB Modem Control Option
  ...be connected to [[modem]]s. It could be set to [[interrupt]] the [[Central Processing Unit|CPU]] when a modem control line (Ring, Carrier, etc) changed state. *DTR - Data Terminal Ready; allow modem to enter data mode
  7 KB (975 words) - 04:15, 18 February 2023
• KA650 CPU
  {{InfoboxVAXCPU-Data The '''KA650''' is the [[Central Processing Unit|CPU]] used in several [[Digital Equipment Corporation|DEC]] [[MicroVAX
  3 KB (369 words) - 08:32, 12 September 2023

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