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The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used the UNIBUS for main memory access (although a built-in cache was standard).

It consisted of a custom 14-slot backplane, and 6 hex boards:

  • uWord (M7872)
  • Decode (M7873)
  • Data Path (M7874)
  • KT/Cache (M7875)
  • Timing (M7876)
  • Status (M7827)

for the basic CPU, held in slots 2-7 of the backplane.

It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.

A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.

The remaining slots, 12-14, were SPC slots.


It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 212 words, divided into 8 blocks. The allocation of the blocks was:

  1. Base instructions
  1. Console an Error log
  2. EIS, Initialization
  3. Floating point
  4. Floating point
  5. ECS
  6. ECS/UCS
  7. ECS/UCS