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• Installing Ultrix 4.5 on SIMH
  ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
  44 KB (6,192 words) - 09:30, 29 September 2023
• Installing 4.1 BSD on SIMH
  ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames
  7 KB (1,100 words) - 07:32, 2 February 2016
• Installing 4.1c BSD on SIMH
  We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes
  13 KB (2,077 words) - 16:30, 7 August 2017
• SS-50 bus
  * &phi;1: The Phase 1 output from the two-phase non-overlapping clock of the processor * <u>&phi;2</u>: The inverted Phase 2 output from the two-phase non-overlapping clock of the processor, used to indicate the presence of va
  6 KB (1,084 words) - 16:55, 16 February 2024
• KT11-B Paging Option
  *11 - Non-Simple reference (phase 1) *12 - Non-Simple reference (phase 0)
  15 KB (2,571 words) - 22:23, 11 October 2022
• KT11-B Technical Manual
  * PGM(13) (10-1): Window access (phase 1)? * PGM(14) (10-1): Window access (phase 0)?
  31 KB (4,983 words) - 18:22, 2 July 2023
• TE16 DECmagtape Transport
  ...pe density = 800 bpi ([[Non Return to Zero Inverted|NRZI]])<br>1600 bpi ([[Phase Encoded|PE]])
  5 KB (729 words) - 17:48, 20 April 2024
• TM03 magtape controller
  ...(125 IPS). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).
  2 KB (366 words) - 18:41, 22 May 2022
• TM02 magtape controller
  ...r second). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).
  2 KB (345 words) - 18:27, 22 May 2022
• BCPL
  ...ne-independent intermediate language called OCODE, generated by the second phase, into the target machine's [[object code]]. Porting the compiler involved writing a new third phase; compiling that with the existing compiler on the host machine, producing a
  3 KB (542 words) - 07:42, 20 June 2023
• RP04 disk drive
  | power consumption = 660 VA per phase (running); 3300 VA per phase (starting, 10 seconds max)
  2 KB (284 words) - 19:38, 23 December 2023
• RP03 disk drive
  | power consumption = 660 VA per phase (running); 3300 VA per phase(starting)
  2 KB (233 words) - 20:45, 10 February 2024
• RC11 disk controller
  ...ss Found || Clock Polarity || DMA Enable || Data Track || Address Track || Phase Lock || Address Mark || Data Mark || Clock Track
  3 KB (372 words) - 03:14, 10 December 2021
• OMNIBUS
  ...core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.
  2 KB (325 words) - 04:52, 19 September 2021
• 861 Power Controller
  * 861-A - 110V two-phase, 4-prong twist plug NEMA L14-20P * 861-B - 220V single-phase, 3-prong twist plug NEMA L6-20P
  1 KB (176 words) - 04:14, 16 June 2022
• FCO CIBCI-I001
  on a 9 Track, 1600 BPI Phase Encoded Tape-Drive (i.e. TE16,
  49 KB (4,759 words) - 09:21, 27 February 2023
• Superfoonly
  ...t was an order of magnitude faster than the existing [[KA10]]. The design phase was finished and projected to meet the goal, but at that point [[Defense Ad
  1 KB (180 words) - 21:48, 6 January 2024
• Bus Arbitration on the Unibus and QBUS
  ..., two flip-flops will add between 50ns and 100ns of delay depending on the phase relationship of the incoming bus grant with the clock, well within the spec
  21 KB (3,685 words) - 04:35, 28 November 2023
• Digital Data Communications Message Protocol
  ...nally designed by [[Digital Equipment Corporation|DEC]] for the [[DECnet]] Phase I network [[protocol suite]], in 1974. It was retained in later versions of
  5 KB (747 words) - 18:15, 29 September 2023
• Installing UTX/32 2.1B on SIMH
  == Phase 1 / tape boot ==
  5 KB (716 words) - 04:20, 31 August 2021

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