PDP-11 Memory Management

PDP-11s which provide memory management use a standard PDP-11 Memory Management architecture. It provides several different operating modes for the CPU: Kernel, Supervisor, and User; each mode has its own set of memory management settings.

When memorymanagement is enable, the basic 64 Kbyte address space of the PDP-11 architecture is divided into 8 segments, each of which can be set to any length between 0 bytes and 8 Kbtes, in 0100 (64.) byte increments.

An additional enhancement is that instruction and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called Split I+D space capability; this increases the memory available to the operating system and each user to 128 Kbytes.

Registers

The memory management is entirely controlled by groups of registers in the CPU.

Each segment (48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register. Their addresses are:

Address	Name	Function
772200	SID0	Supervisor I-Space PDR #0
...
772216	SID7	Supervisor I-Space PDR #7
772220	SDD0	Supervisor D-Space PDR #0
...
772236	SDD7	Supervisor D-Space PDR #7
772240	SIA0	Supervisor I-Space PAR #0
...
772256	SIA7	Supervisor I-Space PAR #7
772260	SDA0	Supervisor D-Space PAR #0
...
772276	SDA7	Supervisor D-Space PAR #7
772300	KID0	Kernel I-Space PDR #0
...
772316	KID7	Kernel I-Space PDR #7
772320	KDD0	Kernel D-Space PDR #0
...
772336	KDD7	Kernel D-Space PDR #7
772340	KIA0	Kernel I-Space PAR #0
...
772356	KIA7	Kernel I-Space PAR #7
772360	KDA0	Kernel D-Space PAR #0
...
772376	KDA7	Kernel D-Space PAR #7
777600	UID0	User I-Space PDR #0
...
777616	UID7	User I-Space PDR #7
777620	UDD0	User D-Space PDR #0
...
777636	UDD7	User D-Space PDR #7
777640	UIA0	User I-Space PAR #0
...
777656	UIA7	User I-Space PAR #7
777660	UDA0	User D-Space PAR #0
...
777676	UDA7	User D-Space PAR #7

In addition, there are four registers which control the overall operation of the memory management.