Camintonn CMV-504
The Camintonn CMV-250, CMV-500, CMV-254 and CMV-504 are a series of QBUS memory cards, in dual QBUS card-size format, with capacities of 256 Kbytes, 512 Kbytes, 1 Mbyte and 2 Mbytes, respectively. They all use the same PCB, and have capacities of 128-512 Kbytes when using 64Kx1 DRAMs, or 512 Kbytes - 2 Mbytes (using 256Kx1 DRAMs).
The board was normally sold with 1, 2, or 4 rows of chips. (Interestingly, there must be two ways to produce a CMV-500 - 1 row of 256Kx1 parts, or 4 rows of 64Kx1 parts. An example of the latter has not been spotted as of yet.)
Configuration
No original Camintonn documentation is currently available; configuration information is therefore provided here.
For Q18 operation: jumper "A" is installed; for Q22 operation: jumper "B" is installed instead.
For parity CSR enabled: jumper "C" is installed; for parity CSR disabled, jumper "D" is installed instead.
For a 4KW I/O page: jumper "K" is installed; for a 2KW I/O page, jumper "L" is installed instead.
For QBUS Block Mode enabled: jumper "T" is installed; for QBUS Block Mode disabled, jumper "S" is installed instead.
The Parity CSR address is controlled by jumpers G-H and J (I = jumper installed; R = jumper removed).
| Address | G | H | J |
|---|---|---|---|
| 17772100 | I | I | I |
| 17772102 | I | I | R |
| 17772104 | I | R | I |
| 17772106 | I | R | R |
| 17772110 | R | I | I |
| 17772112 | R | I | R |
| 17772114 | R | R | I |
| 17772116 | R | R | R |
Address Configuration
The starting address is controlled by jumpers 1-9, 15 and 16:
| Address | J1 | J2 | J3 | J4 | J5 | J6 | J7 | J8 | J9 | J15 | J16 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0KB | I | I | I | I | I | I | I | I | I | I | R |
| 128KB | I | I | I | I | R | R | R | R | R | R | I |
| 256KB | I | I | I | I | I | R | R | R | R | R | I |
| 384KB | I | I | I | I | R | I | R | R | R | R | I |
| 512KB | I | I | I | I | I | I | R | R | R | R | I |
| 640KB | I | I | I | I | R | R | I | R | R | R | I |
| 768KB | I | I | I | I | I | I | R | R | R | R | I |
| 1024KB | I | I | I | I | I | I | I | R | R | R | I |
| 1536KB | I | I | I | I | I | I | R | I | R | R | I |
| 2048KB | I | I | I | I | I | I | I | I | R | R | I |
| 2560KB | I | I | I | I | I | I | R | R | I | R | I |
| 3072KB | I | I | I | I | I | I | I | R | I | R | I |
| 3584KB | I | I | I | I | I | I | R | I | I | R | I |
Jumpers 1 through 4 control starting addresses of 8KB, 16KB, 32KB, and 64KB respectively: thus a board starting at 8KB would have all jumpers removed except J16.
The ending address is controlled by jumpers 10-14:
| Address | J10 | J11 | J12 | J13 | J14 |
|---|---|---|---|---|---|
| 128KB | R | R | R | R | R |
| 256KB | I | R | R | R | R |
| 384KB | R | I | R | R | R |
| 512KB | I | I | R | R | R |
| 1024KB | I | I | I | R | R |
| 1536KB | I | I | R | I | R |
| 2048KB | I | I | I | I | R |
| 2560KB | I | I | R | R | I |
| 3072KB | I | I | I | R | I |
| 3584KB | I | I | R | I | I |
| 4096KB | I | I | I | I | I |
Dual-chip capability
The CMV-2xx/-5xx series has the ability to use either 64Kx1 DRAMs or 256Kx1 DRAMs, using a set of jumpers which are not covered in the available documentation.
Down near the fingers, there are a block of 6 solder pads, denoted thus:
MPR
NOS
(Note that there is another 'S' jumper on the board, at the top.)
Available documentation describes them as "Starting and ending address boundary" (but without giving any detail as to their operation).
One version of the board, configured for 256Kx1 chips, has jumpers on M-N, P-R, and etch cuts on R-S, N-O (the inverse of which is likely the configuration for 64K chips, although this has not been verified).
Another variant of the board, also using 256Kx1 chips, has a slightly different PCB (likely a later revision), and has no jumpers, but has etch connections M-N, P-R (note - the same as the previous board has jumpers).
References
"SMS 1000 Microcomputer System Models 40, 41 and 50 OEM Manual", February 1987, Scientific Micro Systems, Inc.; pages 4-37 to 4-47
