DQ11 NPR Synchronous Line Interface

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The DQ11 is the earliest DMA synchronous serial line interface for the UNIBUS. The base unit, the DQ11-DA/EA, was double-buffered, and used separate receive and transmit interrupts to signal completed transfers of data. One optional expansion, the DQ11-AB, provided CRC computation in hardware for error detection; any CRC algorithm could be configured. Another optional expansion, the DQ11-BB, provided programmable character detection in hardware, for functions such as DLE stuffing.

It provided an EIA RS-232 interface (to Bell 200 series modems, such as the model 201, and equivalents), and optionally a current loop interface (to Bell 300 series modems, such as the model 303, and equivalents). Baud rates of up to 10K bits/second were supported by the EIA interface, and up to 1M bits/second by the current loop interface.

The character length (up to 16 bits), the sync character, idling (sending the sync character), and discarding additional incoming sync characters were configurable under program control, as could modem control leads. It could operate in either half-duplex or full-duplex mode. Switches allowed configuration of per-character parity (even or odd) for error detection, and whether one or two contiguous sync characters were used.

The DQ11 supported byte-oriented protocols, e.g. BISYNC. Optionally, the DQ11-KA allowed use of an internal clock (when two interfaces were connected directly, without modems).

Registers

Register Abbreviation Address
Receive Status Register DQRxCSR 76xxx0
Transmit Status Register DQTxCSR 76xxx2
Reg/Err Register DQRER 76xxx4
Shadow Register(s) DQSR 76xxx6

The addresses shown are for the first DQ11 in a system's floating device address space; additional ones are normally set to be immediately following.

The DQ11 has a set of 16 'shadow' registers, access to which is gained by placing the shadow register number in the appropriate bits in the DQRER, and then reading/writing the DQSR. (The DQ11 documentation refers to these as 'secondary' registers, but this is confusing, as the shadow register set contains "primary" and "secondary" registers; the term 'shadow' has therefore been adopted here to be non-duplicative.) The shadow registers are:

Register Function
0 Receive Bus Address - RxBA (Primary)
1 Receive Character Count - RxCC (Primary)
2 Transmit Bus Address - TxBA (Primary)
3 Transmit Character Count - TxCC (Primary)
4 Receive Bus Address - RxBA (Secondary)
5 Receive Character Count - RxCC (Secondary)
6 Transmit Bus Address - TxBA (Secondary)
7 Transmit Character Count - TxCC (Secondary)
10 Character Detect - CHARDET
11 Sync Character - SYNC
12 Miscellaneous - MISC
13 Transmit Buffer - TxBUF
14 Sequence - SEQ
15 Receive Block Check Character - RxBCC
16 Transmit Block Check Character - TxBCC
17 Receive/Transmit Polynomial - RTP

76xxx0: Receive Status Register (DQRxCSR)

CHARF USROPT RACT CHARDET RxDNP RxDNS RxDNIE CHARIE HD RxP/S STRS RxGO
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • CHARF - Character Flag
  • USROPT - User Option
  • RACT - Receive Active
  • CHARDET - Character Detected
  • RxDNP - Receive Done Primary Flag
  • RxDNS - Receive Done Secondary Flag
  • RxDNIE - Receive Done Interrupt Enable
  • CHARIE - Character Interrupt Enable
  • HD - Half Duplex
  • RxP/S - Receive Primary/Secondary
  • STRS - Strip Sync
  • RxGO - Receive Go

76xxx2: Transmit Status Register (DQTxCSR)

DSF USROPT CS CARR RING DSR DTR RS TxDNP TxDNS TxDNIE DSIE ERRIE TxP/S IDLE TxGO
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • DSF - Data Set Flag
  • USROPT - User Option
  • CS - Clear to Send
  • CARR - Carrier or Signal Quality Detector
  • RING - Ring Indicator
  • DSR - Data Set Ready
  • DTR - Data Terminal Ready
  • RS - Request to Send
  • TxDNP - Transmit Done Primary Flag
  • TxDNS - Transmit Done Secondary Flag
  • TxDNIE - Transmit Done Interrupt Enable
  • DSIE - Data Set Interrupt Enable
  • ERRIE - Error Interrupt Enable
  • TxP/S - Transmit Primary/Secondary
  • IDLE - Idle Mode
  • TxGO - Transmit Go

76xxx4: Reg/Err Register (DQRER)

ERRINT MXEET WEN SHREG RxVRCE RxBCCE RxNXM TxNXM RxLE TxLE RxCLE TxCLE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • ERRINT - Error Interrupt
  • MXEET - Memory Extension or Enter/Exit T
  • WEN - Write Enable for bits 13/14
  • SHREG - Shadow Register Pointer
  • RxVRCE - Receive Vertical Redundancy Check Error
  • RxBCCE - Receive Block Character Check Error
  • RxNXM - Receive Non Existent Memory Error
  • TxNXM - Transmit Non Existent Memory Error
  • RxLE - Receive Latency Error
  • TxLE - Transmit Latency Error
  • RxCLE - Receive Clock Loss Error
  • TxCLE - Transmit Clock Loss Error

Implementation

It was constructed from a number of smaller FLIP CHIPs, along with several larger boards, which were installed in a custom 4-slot backplane system unit (DEC part number 70-09467). Installation of the DQ11-AB or DQ11-BB required an additional 4-slot backplane (part number 70-09468), connected to the first one via 3 BC08S flat cables connected to M971 Cable Connector cards. (Cards plugged into those slots in the DQ11-AA had to be moved to the second backplane.) The DQ11 used one of the DF11 Communications Line Adapter‎s to interface to the modem.

The modules for the basic unit are:

  • M105 - UNIBUS Address Selector Module
  • M7821 - Interrupt Control
  • M7812 - Bus selectors, CSRs, shift registers
  • M7813 - Character count, bus address, shift control
  • M7815 - Modem control
  • M7818 - Hardwired character detection and NPR control

The EIA interface (DQ11/DA) includes:

  • M594 - EIA Level Converter Module

The 20 mA interface (DQ11/EA) includes:

  • M595 - 20mA Converter Module

The modules for the options are

  • M7816 - Block check (DQ11-AB)
  • M7817 - Programmable character detection and sequence control (DQ11-BB)
  • M4050 - Crystal Clock Module (DQ11-KA)

The M7812, M7813, M7816 and M7817 are hex cards; the M7818 is dual, and the M7815, M105 and M7821 are single. (All are extended length.)

Board locations (as seen from the board insertion side of the backplanes, not the wire-wrap pin side, as is common in DEC documentation) are (main backplane):

Connector
Slot A B C D E F
1 UNIBUS In DF11 Cable DF11 Converter M7815 M105
2 M7812
3 M7813
4 UNIBUS Out M7821 M4050@ M7818@

@ = M971/BC08S if DQ11-AB/DQ11-BB installed.

Board locations (DQ11-AB/DQ11-BB backplane):

Connector
Slot A B C D E F
1 UNIBUS In M4050 M971/BC08S M971/BC08S M971/BC08S
2 M7816
3 M7817
4 UNIBUS Out Unused M7818

See also

External links

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