Talk:KL10

MC at LCM

I thought MC went to Sweden; how did it end up at the LCM? Jnc (talk) 16:23, 24 June 2019 (CEST)

That's right, it did. It remained for many years in Peter Löthberg's storage. But last year most of the computers there, including MC, was moved to LCM. Larsbrinkhoff (talk) 19:47, 24 June 2019 (CEST)

Figured; didn't his KI10 wind up there too? Jnc (talk) 21:29, 24 June 2019 (CEST)

Yes, parts of the dual and sometimes triple processor "KICKI". And also KATIA (literally "KA-10" in Swedish), a CADR, and some other goodies. Well worth a visit if you're in town; ask for the basement tour. Larsbrinkhoff (talk) 07:01, 25 June 2019 (CEST)

Microword

Someone who looked at the schematics claims the microword width was 75 bits on the model A, and 76 on the model B. The additional bit is used to implement an improved CALL instruction. Larsbrinkhoff (talk) 07:29, 6 July 2019 (CEST)

Yeah, I vaguely recall something like that.

I really wish there was a single document one could consult which covered all the variants, and gave the differences, but no, it seems like one has to read through everything that's left to find it all. And then there are things like the S-Bus/X-Bus switch; it would be nice to have something which says what the differences are (surely such a doc would have been useful BITD; for people who already know the S-Bus, read that, and you're done), but it looks like we're going to have to read the descriptions of both, and work out what changed. Sigh. Jnc (talk) 15:54, 6 July 2019 (CEST)

Version confusion

So EK-0KL20-IN-001 ("KL10-Based DECSystem-20 Installation Manual") gives, in Section 10.2 "KL10-PV Upgrade Procedure for KL10-C" instructions which clearly include the replacement of the main CPU backplane. However other documents make it sound like the Model B supports multiple sections. So now I'm completely confused as to the whole multi-section thing; I thought it came in with the Model E (AKA KA10-PV), and needed a different CPU backplane, but maybe not? Is the KL10-E different physically from the Model B, or not? Jnc (talk) 01:05, 7 July 2019 (CEST)

E.g. in AD-H391A-T1 ("DECSystem-10/DECSystem-20 Processor Reference Manual"), it says (pg. 1-2) "The {KL10} exists in two versions, with and without extended addressing". So maybe the Model B supports sections? So is a 'KL10-C' a Model A processor? If not, why does the KL10-PV upgrade need to replace the CPU? Very confusing. Jnc (talk) 01:20, 7 July 2019 (CEST)

As further data, the "1080, 2040, 2060 Engineering Functional Spec" discusses sections, so it sounds like the Model B supported sections from the start? Or perhaps the hardware had the necessary support, but it needed upgraded microcode which was not available at the initial Model B release. (It's not clear if that document refers to the Model A or not; given the discussion in there of the RH20, not present on the Model A, probably not. Then again, since the 1080 apparently used a Model A - the model numbers are confusing too - who knows?) FWIW, the ucode version history shows that section support was added starting in rev 201 ("BEGIN EXTENDED ADDRESSING CHANGES IN EARNEST"). Jnc (talk) 01:57, 7 July 2019 (CEST)

I also think it's confusing, but the way I have seen people talk about this, my theory is these are one set of models: KL10-PA, KL10-PV, and KL10-PW. I believe the first is the non-extended, and the second to have extended addressing. The last one has a bigger cache.

Then there is another set of models: KL10-A, KL10-B, KL10-C, KL10-D, KL10-E, KL10-R. A/B/C had KL10-PA, the others PV or PW.

Finally "model A" and "model B" is yet another thing. Model A is the KL10-PA without extended addressing, with a "model A backplane", and just 1280 words of microcode store. Model B had extended addressing, another backplane, and 2048 words. Larsbrinkhoff (talk) 10:23, 7 July 2019 (CEST)

Yeah, clearly there are multiple 'namespaces' involved, and my thinking has been on roughly the same lines (with the three you mention). Some differences in the details, though...

E.g. in EK-0KL10-02 Part 1 (no title, seems to be notes for F/S) pg. 9, it says a 1090 can be a "KL10-B(PA) or KL10-D(PV)", and in the next table down, it says a KL10-B is PV=no, but has RH20's. So now I'm really confused, since I thought the RH20's needed the modified backplane of the model B.

Speaking of which, a note at the bottom of the page says that a PA is a 'Model A', and describes it as having "internal channels". The PV is a 'Model B' (extended addressing, larger ucode, faster clock). So maybe the Model A backplane can support RH20's, but something (e.g. CPU board set) doesn't allow that in the KL10-A (the table shows the KL10-A with "No" for "Int Chan" - C Bus and RH20s, I assume).

The tables show the KL10-A, -B and -C as "PA", with the -D and -E as "PV". (Any idea what 'PV' stands for?) I think I may just include that table to show what the -A through -E mean.

As to the cache, EK-OKL10-TM ("KL10-Based Technical Manual") has an Appendix A "MCA25 KL Cache/Paging Upgrade", which focusses on what it does, but it sounds like that cache was an upgrade to the PV. So I'm not sure the PW is fundamentally different, although maybe it is a DEC product code for a Model B with MCA25 pre-installed. Jnc (talk) 19:13, 7 July 2019 (CEST)

For additional hilarity, in this page I found::

"Model-C backplane" with 4096 words cache and double pager buffer (1024 instead of 512). Existing 1091 and 2060 systems could be upgraded to 1095 and 2065 by installing the "Model-C" modifications.

although I'm a bit dubious about the new backplane part; the specs seem to be those of the MCA25 (above), from which it's clear that there had to have been new boards, at least, though.

(This page says "The designation is KL10-RH, which confirms it had the final MCA25 cache/pager upgrade.")

That first page also says "KL10-R = same as KL10-E, but in FCC approved cabinets", but then goes on to say "The KL10-R has a 'Model-C backplane' with 4096 words cache and double pager buffer (1024 instead of 512)", which agrees with the above.

Since these are all personal sites, I'm reluctant to rely too much on them, though. Wish we could find more on the MCA25 hardware... Jnc (talk) 15:20, 8 July 2019 (CEST)

Looking at the images in the (Corestore page, I'm wondering if the difference between the KL10-A (no RH20s) and the KL10-B (same Model A CPU, RH20s) is just the wiring (i.e. no cable ports for MASSBUS)? Or maybe it's the MBox I/O backplane? Either could explain the -A/-B difference that's so confusing me. Jnc (talk) 16:41, 8 July 2019 (CEST)

Also, the Shiresoft KL10 page has an image which shows all the connectors from the MBoxI/O backplane, which allows one to tell (on the Corestore image which shows how they are wired) what functionality was where on the MBoxI/O backplane. Now if only we had an image of a KL10-A MBoxI/O backplane! Jnc (talk) 16:51, 8 July 2019 (CEST)

Turns out there is one in EK-108OU-PD-002, "KL10-Based Physical Description", pg. 3-7. Jnc (talk) 19:54, 12 July 2019 (CEST)

Well, between Eric's help, and careful perusal of the docs, I think we're getting there. There are a few points still un-answered, but I'm not sure we'll get answers to those unless we can ask one of the KL10 engineers. Jnc (talk) 19:03, 11 July 2019 (CEST)

Yes, this is already much better than anything else online (except possibly if digging into PDFs). Thanks! Larsbrinkhoff (talk) 15:56, 12 July 2019 (CEST)

I just added another section, to describe the physical construction, and put in some details about which I/O functions were on which backplanes in the I/O cabinet. I think I'm just about done for the moment; I plan to add a bit more about the S-X/Bus stuff, once I re-read the upgrade instructions (in the MF20 manual), and then that'll be it. Jnc (talk) 19:54, 12 July 2019 (CEST)

S-Bus/X-Bus differences

So I've been reading the MF20 Technical Manual, and in section 1.1.2.4, "KL10 CPU Modifications" (pg. 1-4) it says:

uses an improved version of the KL10's SBus called the XBus .. the M8519 SBus translator modules in slots 7 and 8 of the CPU backplane must be replaced .. 1. Core/MOS mixed configurations use two M8580 modules .. 2. MOS-only configurations use two M8581 modules ..

So far, so good; this corresponds to what Eric explained.

However, in 9.12.1 "M8570 Memory Module" (pp. 9-10/9-13) it says:

All data entering or leaving the MOS array is buffered by a set of DC008 data mux chips ...perform the dual functions of: .. 2. ECL to TTL translation for a write, and TTL to ECL translation for a read.

So now I'm completely confused; I though the XBus was TTL, replacing the ECL of the SBus? So why the ECL translation above? Unless the internal logic of the MF20 uses ECL, and the MOS chips use TTL? But if so, why change to the XBus?

I may have to ask Eric what's going on. Jnc (talk) 15:16, 14 July 2019 (CEST)

KL10 bus names, connectors

The KL10-Based Physical Description gives some interesting info on the names of, and connectors used for, the external memory and I/O busses in the KL. The memory is the KBus; the I/O is the IBus, and it uses the same QuickLatch connectors as the KBus. So in the image of the bus connectors, 4 are KBus (makes sense, since the KL can do 4-way interleave), and 2 are IBus (which I don't quite understand). Jnc (talk) 17:45, 20 April 2021 (CEST)

TENEX

Is there any more information about KL10 TENEX? I checked Murphy's "Origins", but I didn't see anything there. Larsbrinkhoff (talk) 21:37, 8 March 2022 (CET)

I kind of have the vague impression that everyone with a KL10 ran TOPS-20; it was likely free with a KL10, and TOPS-20 was basically an upgraded TENEX. If you want to confirm, look in a late HOSTS.TXT (although it may not distinguish the exact PDP-10 model). Jnc (talk) 01:18, 9 March 2022 (CET)

What I was kind of fishing for was whether there really was a KL10 TENEX at all, out in the wild outside DEC. But now I found an Arpanet Resources Handbook from 1978 that clearly says USC-ECL was a KL10 running TENEX, so that's settled. Larsbrinkhoff (talk) 14:13, 28 March 2022 (CEST)

I also contacted former USC staff James Pepin and James Wiedel, who confirmed ECL ran TENEX on a KL10 (and a KI10 before that). Larsbrinkhoff (talk) 08:04, 18 August 2022 (CEST)

Clock speed

So EK-0KL10-02 says "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock". The info block only lists a single clock speed. I went looking, and in EK-1080U-SD-003, which I am currently mining for useful stuff, I find (pg. SYS1/4-10) "master clock which runs at 50 MHz in the model A CPU and 58 MHz in the model B CPU" (blast, that PFDF doesn't include OCR; had to type the quotation). Eureka! Jnc (talk) 14:56, 12 November 2023 (CET)

Interesting, I got 25/30 MHz in http://pdp10.nocrew.org/cpu/processors.html, but since I wrote that decades ago I don't know the source. Larsbrinkhoff (talk) 15:09, 12 November 2023 (CET)

I wonder if that 50 MHz means that it does one uinstruction every 20 nsec, or does the uprocessor use more than one clock cycle per uinst? That could explain that factor-of-two difference. I'm not up for studying the KL10 Tech manual to work out the answer, though! It does say (Section 3.2.1.1) "30 MHz clock to the MBox, a 12.5 MHz clock to the EBox control store", which makes it sound like the uprocessor does not run at the full clock rate. That might be your answer. Jnc (talk) 16:10, 12 November 2023 (CET)

OZ configuration

Date: 21 March 1982 03:09-EST
From: Xxxxxx Xxxxx Xxxxxx <XXXX at MIT-AI>
Subject:  (current-state-of-OZ?)
To: BUG-OZ at MIT-AI

[...]

As many people have noticed, OZ has arrived. The configuration is as
follows:

8  RP06 disk drives, 176 megabytes per drive.
2  TU77 tape drives. 1600 bpi maximum density.
   (We hope to get a 6250 bpi tape drive, because backing up our disks
    would require too much tape otherwise)
1  DecSystem 2060. Comes in 4 cabinets; I/O, Front End, CPU, and
   External Memory Cabinet.
1 DN20 for terminal interface.
1 AN20 for Arpanet interace.

The electricians should be done about next Tuesday; DEC could probably
come next Wednesday and begin installation. I would suspect that the
machine could be up for use by Lab members who want to test it out in
2 or 3 weeks.

Optional cache

There are a variety of sources that indicate that the original KL cache (the MCA20) was optional; I was somewhat dubious about that (below), but it turns out it's true: the MCA20 Field Maintenance Print Set has a 'Module Location Chart' on pg. 3 which has a "Channel no Cache" column. So I guess it's correct - one apparently really could get a KL10-C without a cache!

The 'Channel' probably refers to the CBus, needed for the RH20. There is no 'No Channel no Cache' column in that table; I wonder if that configuration couldn't work (I can't offhand see why it wouldn't, but I have not studied the issue), or just that they didn't offer it?

The reason I didn't think the MCA20 could be optional is because there are actually two completely separate caches in the KL (actually, KL10 Tech Manual says there are four - in A.1 - but I have no idea what the other two are) - the 'main memory' cache (used for instructions, operands, etc) and the 'paging' cache (used for page table entries). The MCA25 replaces them both, so I assumed that the MCA20 contains them both, too - which would make it effectively non-optional - because without the cached page table entries, each paged memory reference would take several memory cycles (the KL10 TM says five - Section A.3 - but I can only think of three: the UPT pointer to the page table, the page table entry, and then the actual memory reference) cutting the effective memory bandwidth by 5/6, which is clearly unreasonable. The answer is that the MCA20 contains the 'main memory' cache only (although I have to confirm that by looking at KL10 MBox prints to confirm that the 'paging' cache is there).

Should we have an MCA20 page which explains this? It would be pretty easy to do - most of the content is already here! :-) Jnc (talk) 13:35, 13 November 2023 (CET)

Sure, why not! Larsbrinkhoff (talk) 18:12, 13 November 2023 (CET)

Front end backplanes

The backplanes in the KL10 front end shown here are (in the image that shows the pin side of the backplanes, from the left):

• KD11-A CPU (9-slot)
• MM11-U core memory (9-slot)
• RH11 MASSBUS controller (9-slot)
• 2 * DD11-C backplane (4-slot)

The first 3 are probably a standard set; not sure about the DD11-C's. MIT-MC's included at least one DH11. Jnc (talk) 00:03, 3 April 2024 (CEST)