Series 16

The Series 16 (members of which were usually denominated as DDP-x16) was a family of 16-bit minicomputers, produced by Computer Control Corporation (later bought by Honeywell, which continued to sell them for some years). They were intended for use in scientific and real-time control applications. Types in the series were (in chronological order):

Model	Cycle time	Technology
116	1.7 µsec	discrete transistors
416	0.96 µsec	integrated circuits
516	0.96 µsec
316	1.6 µsec
716	1.6 µsec

Programming details varied from type to type (although the -116 and -516 were seemingly program compatible; the -526 and -316 definitely were program compatible). The DDP-416 was apparently a cost-reduced version of the DDP-516, and lacked the B and X registers (below), along with numerous instructions. Little is known of the -716 (not much documentation on it has survived; it was apparently not a commercial success), but it apparently tried to fix some of the gaps in the earlier machines; e.g. it had support for stacks (including a stack pointer in hardware).

All used core memory for their main memory. They came with a base amount of 4K words (1K in the -116); additional banks of 1K (in the -116), 4K, 8K or 16K (in the -516) were also available. The maximum was supported was 16K, but an "Extended Memory Addressing" option allowed this to be doubled to 32K. Parity on main memory was available as an option. Multiply and divide hardware/instructions were optional (normalization came with these).

Peripherals available included: high-speed paper tape reader and punch, punched card reader and punch, line printer, magnetic tape drive, and fixed head and moving head disks. Parallel ports (input-only, output-only, or bi-directional) were also available.

The most well-known use of Series 16 computers was as Interface Message Processors in the ARPANET; originally Honeywell 516s (the ruggedized version thereof) and 316s. Early Prime computers, including the Prime 200, were also ISA clones of the DDP-516.

Architecture

All were load-store architecture machines. Main memory on the machines, as seen by the CPU, was divided into 'sectors' (each 512. words long); memory-reference instructions could directly access only two sectors (see below). The machine had one condition code, 'C' (for carry), held in a 'flag' register.

Input/output was organized around a single bus, to which the CPU and peripherals were attached. Main memory was attached to a separate bus in the CPU. Interrupts (which could be disabled under program control) were supported, at a single level of priority (multiple levels were available as an option). Each interrupt had a unique interrupt vector in main memory, which contains the address of the handler.

Two kinds of DMA were available:

• DMC ('Direct Multiplex Control') - data was transferred using the standard I/O bus (above). It was similar to DEC's three cycle data break, as the buffer's current address and end location were held in main memory; each DMC cycle therefore required four memory cycles.
• DMA ('Direct Memory Access' - occasionally called DDC 'Direct Data Channel', e.g. in the 116 documentation) - an alternative, special bus was used. Dedicated registers in the device controller held the current buffer address and end; each DMA transfer thus required only one memory cycle. DMA transfers did not wait for completion of an instruction; instructions which used multiple cycles (such as shifts and multiply and divide instructions) could be interleaved with DMA cycles.

Registers

The machine has 4 visible main registers:

• a program counter, 'P';
• an accumulator, 'A';
• an auxiliary register, 'B' (paired with 'A' for double precision mode);
• an index register, 'X'.

The X register shadows main memory location zero on all Series 16 machines; the A register similarly shadows location 1, and the B register shadows location 2.

Instruction layout

The basic instruction layout for Series 16 machines was that used for 'memory reference instructions' (the main group of instructions):

Indirect	Index	Opcode				Sector	Address
15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00

Other instructions were worked into the gaps left by these; see Series 16 instructions for the details.

Memory reference instructions could reference i) words in the 'base' sector (normally sector 0), or ii) words in the same sector as that containing the instruction - the choice being controlled by the 'Sector' bit. (An option, "Memory Lockout", was available, which allowed the base sector to be relocated; this was utilized in time-sharing operation.)

The 'Indirect' bit was also called the 'Flag' bit; the 'Index' bit was also called the 'Tag' bit; these became part of the opcode in non-memory-reference instructions. If both were set in an ordinary instruction, indexing took place before indirection. The indirect address, if used, allowed access to all locations in memory. The indirect address word also had Flag and Tag bits; normally, there was no limit to the number of levels of indirection that could be invoked.

External links

• ComputerControlCompany - documentation at Bitsavers (extensive)
• ddp-116
• The 3C Legacy Project
• Honeywell Series 16 - fairly complete documentation archive, along with much else
  • Micro-coding the DDP-516 Computer - ('microcoding' in the same sense as in the PDP-8)
• Honeywell DDP-116
• Theo Engel's DDPx16 pages
• H316 Home - includes images of a ruggedized -316
• Decoding The H316/H516 “Generic A” Instructions