Series 16 instructions are basically the same across all models of the Series 16 line (although some are missing on some models).
Most of the instructions are fitted into a basic layout used for the memory reference instructions; specifically, the basic opcode field is in the same place in all of them (although some instructions 'borrow' bits from other fields).
Memory reference instructions
| Indirect |
Index |
Opcode |
Sector |
Address
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
Memory reference instructions can reference i) words in the 'base' sector (normally sector 0), or ii) words in the same sector as that containing the instruction - the choice being controlled by the 'Sector' bit. (An option, "Memory Lockout", is available, which allows the base sector to be relocated; this is utilized in time-sharing operation.)
The 'Indirect' bit is also called the 'Flag' bit; the 'Index' bit is also called the 'Tag' bit; these become part of the opcode in non-memory-reference instructions. If both are set in an ordinary instruction, indexing takes place before indirection. The indirect address, if used, allows addressing of all locations in memory. The indirect address word also has Flag and Tag bits; normally, there is generally no limit to the number of levels of indirection that can be invoked.
| Opcode |
Mnemonic |
Action
|
| 0 |
Generic and skip/shift (below)
|
| 1 |
JMP |
Jump
|
| 2 |
LDA |
Load A
|
| 3 |
ANA |
AND to A
|
| 4 |
STA |
Store A
|
| 5 |
ERA |
XOR to A
|
| 6 |
ADD |
Add
|
| 7 |
SUB |
Subtract
|
| 010 |
JST |
Jump and Store
|
| 011 |
CAS |
Compare
|
| 012 |
IRS |
Increment, replace and skip
|
| 013 |
IMA |
Interchange memory and A
|
| 014 |
Input-output (below)
|
| 015 |
LDX/STX |
Load X/Store X
|
| 016 |
MPY |
Multiply
|
| 017 |
DIV |
Divide
|
Generic instructions
| Opcode
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
| Opcode |
Mnemonic |
Action
|
| 000000 |
HALT |
Halt
|
| 000043 |
INK |
Input keys
|
| 000201 |
IAB |
Interchange A and B
|
| 000401 |
ENB |
Enable program interrupt
|
| 001001 |
INH |
Inhibit program interrupt
|
| 140040 |
CRA |
Clear A
|
| 140100 |
SSP |
Set A sign plus
|
| 140200 |
RCB |
Reset C bit
|
| 140401 |
CMA |
Complement A
|
| 140500 |
SSM |
Set A sign minus
|
| 140600 |
SCB |
Set C bit
|
| 141044 |
CAR |
Clear A, right half
|
| 141050 |
CAL |
Clear A, left half
|
| 141206 |
AOA |
Add one to A
|
| 141216 |
ACA |
Add C to A
|
| 141340 |
ICA |
Interchange characters in A
|
Not all instructions are listed
Skip instructions
| Opcode
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
| Opcode |
Mnemonic |
Action
|
| 100000 |
SKP |
Unconditional skip
|
| 100001 |
SRC |
Skip if C reset
|
| 100040 |
SZE |
Skip if A zero
|
| 100400 |
SPL |
Skip if A sign plus
|
| 101000 |
NOP |
No operation
|
| 101001 |
SSC |
Skip if C bit set
|
| 101040 |
SNZ |
Skip if A non-zero
|
| 101400 |
SPL |
Skip if A sign minus
|
Not all instructions are listed
Shift instructions
| Opcode |
Count
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
| Opcode |
Mnemonic |
Action
|
| 0400 |
LRL |
Long right logical
|
| 0401 |
LRS |
Long arithmetic right
|
| 0402 |
LRR |
Long right rotate
|
| 0404 |
LGR |
Logical right
|
| 0405 |
ARS |
Arithmetic right
|
| 0406 |
ARR |
Logical right rotate
|
| 0410 |
LLL |
Long left logical
|
| 0411 |
LLS |
Long arithmetic left
|
| 0412 |
LLR |
Long left rotate
|
| 0414 |
LGL |
Logical left
|
| 0415 |
ALS |
Arithmetic left
|
| 0416 |
ALR |
Logical left rotate
|
The shift count is given in two's complement form.
Input-output instructions
| Opcode |
Function |
Device
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
| FT |
Mnemonic |
Action
|
| 00 |
OCP |
Output control pulse
|
| 01 |
SKS |
Skip if ready set
|
| 10 |
INA |
Input to A
|
| 11 |
OTA |
Output from A
|
External links
