J-11 chip set

J-11

The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, used in both the KDJ11 CPUs, and a variety of peripherals. It was implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.

It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating point support (using microcode), it can operate with an optional FPJ11 floating point accelerator chip for higher performance.

Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.

External links

• DCJ11 Microprocessor User's Guide (EK-DCJ11-UG-PRE]
• J-11 Programmer's Reference
• J-11 Control Chip Specification
• J-11 Data Chip Specification
• DEC Semiconductor Databook, Volume 1, pp. 261-334
• J-11 (1983)
  • J-11 microcode
• PDP-11/HACK - use of a J-11 in a vintage experiment