DM11 asynchronous serial line interface

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The DM11 asynchronous serial line interface was a very early UNIBUS peripheral which provided up to 16 asynchronous serial line connections. It was in some sense a predecessor to the DH11, in that it used DMA.

However, unlike any other UNIBUS peripheral, much of its internal data was actually stored in main memory, with DMA used to gain access to it, not in registers in the device. (Apparently this was early enough in time that gates for registers were too expensive.) The data stored in memory included:

  • per-line current output buffer address
  • per-line current output transfer length
  • input buffer (circular FIFO buffer)
  • per-line input shift registers

The 64-character FIFO buffer made input over-runs unlikely. There were separate receive and transmit interrupts.

The implementation of the basic DM11-AA used a double custom system unit backplane, containing multiple cards; a flat cable connected this to separate rack-mounted dual-height 'distribution panel' backplane (which required its own independent power supply).

Modular 'line conditioning' units from the DF11 Communications Line Adapter series were installed in the distribution panel to allow support of either 20mA or EIA RS-232 serial lines.

Lines could be connected to modems, provided the correct line conditioning units were installed, but modem control required a DM11-BB Modem Control Option per DM11-AA, mounted in the main DM11 backplane along with the rest of the DM11 cards, and connected to the distribution panel via another flat cable which carried the modem control signals. The DM11-BB is logically a separate device from the DM11-AA, albeit one partially housed in the DM11 backplane.

The line parameters:

  • baud rates (ranging from 50 to 1200)
  • character length (5-8 bits)
  • output stop bits (1 or 2)

were the same for all lines, and set by jumpers.

A 'break' condition on the line (i.e. continuous assertion) could also be generated and detected.

DM11-AA Device registers

Register Abbreviation Address
Status Register DMCSR 775000
Buffer Active Register DMBAR 775002
Break Status Register DMBSR 775004
Base Address Register DMBADR 775006

The addresses shown are for the first DM11-AA11 in a system; additional ones (up to 16 total) are normally set to be at 775010, 775020, etc to 775170.


The DM11-AA boards (all quad, except for the Control C, which is a dual) plugged into the DM11 backplane are:

  • M7240 - Control A
  • M7241 - Control B
  • M7242 - Control C
  • M7243 - Transmitter D
  • M7244 - Transmitter E
  • M7244 - Receiver

and 4 single-width, non-DM11-specific cards:

  • M782 - Interrupt control (two)
  • M105 - Address selection
  • M405 - Clock

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Slot A B C D E F
1 UNIBUS In M7240
2 M105 M7241
3 Power M405 M782 M782 M7242
4 M974 Cable M7245
1   M7244
2   M7243
3 Power Reserved for DM11-BB
4 UNIBUS Out Reserved for DM11-BB

Power comes in on a single-width stub card in the A3 slots (as is canonical in the PDP-11/20 generation of PDP-11s).