Difference between revisions of "DRV11-B Direct Memory Access Interface"
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The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data. | The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data. | ||
| − | It is effectively a [[half duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO. | + | It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO. |
It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s. | It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s. | ||
Revision as of 14:28, 20 April 2020
The DRV11-B Direct Memory Access Interface is a parallel port device controller for the QBUS which provided a pair of 16-bit parallel ports, one input, and one output; it uses DMA to transfer data.
It is effectively a half-duplex device; it has only a single pair of bus address and word count registers. Directional control is by the user's device specifying whether each cycle is a DATI, DATO, or DATIO.
It was a quad format card (M7950); connection to the user's device is via a pair of 40-pin Berg connectors.
Registers
The device has five control and buffer registers, which can be configured to any group of four sequential word locations in the I/O page; the first DRV11-B is normally configured to addresses 772410-72416. The two buffer registers share an address, responding to read or write cycles as the case might be.
| Register | Abbreviation | Address |
|---|---|---|
| Bus Address Register | DRBAR | 767770 |
| Word Count Register | DRWCR | 767772 |
| Control and Status Register | DRCSR | 767774 |
| Input Data Buffer Register | DRINBUF | 767776 (read) |
| Output Data Buffer Register | DROUTBUF | 767776 (write) |
