Difference between revisions of "FP11-F Floating-Point Processor"
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| − | The '''FP11-F Floating-Point Processor''' is the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a single [[DEC card form factor|hex]] card (the M7093), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]]. | + | The '''FP11-F Floating-Point Processor''' is the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a single [[DEC card form factor|hex]] card (the '''M7093'''), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]]. |
The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP each have their own microcode [[Read-only memory#PROM|PROMs]]; 48 [[bit]]s wide in the FPP, and 56 bits wide in the CPU, for a total of 104 bits. | The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP each have their own microcode [[Read-only memory#PROM|PROMs]]; 48 [[bit]]s wide in the FPP, and 56 bits wide in the CPU, for a total of 104 bits. | ||
| − | + | ==External links== | |
| + | |||
| + | * [http://bitsavers.org/pdf/dec/pdp11/1144/EK-FP11F-TM-002_Nov79.pdf FP11-F floating-point processor technical manual] (EK-FP11F-TM-002) | ||
| + | * [http://bitsavers.org/pdf/dec/pdp11/1144/MP00810_FP11F_Jun79.pdf FP11-F Field Maintenance Print Set] (MP00810) | ||
[[Category: PDP-11 Processors]] | [[Category: PDP-11 Processors]] | ||
Revision as of 03:01, 16 January 2022
The FP11-F Floating-Point Processor is the hardware floating point option for the KD11-Z CPU of the PDP-11/44. It implements the full FP11 floating point; it consists of a single hex card (the M7093), which plugs into a dedicated slot in the CPU's backplane.
The CPU and the FPP interact over two tri-state data paths, one for data, and another for the microcode PC. The CPU and FPP each have their own microcode PROMs; 48 bits wide in the FPP, and 56 bits wide in the CPU, for a total of 104 bits.
External links
- FP11-F floating-point processor technical manual (EK-FP11F-TM-002)
- FP11-F Field Maintenance Print Set (MP00810)
