Difference between revisions of "KB11-B CPU"
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| − | The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. | + | The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on the [[PDP-11/45]]'s [[KB11-A CPU]]; the -11/70 is basically an -11/45 with a [[cache]], more [[main memory]], and provision for high/speed [[input/output|I/O]] [[device controller]]s for [[MASSBUS]] devices. |
| − | + | Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a special 32-[[bit]] wide memory [[bus]], the Main Memory Bus, unique to the -11/70, for its bus to main memory; in addition to the speedup of doubling the width, this bus also allowed it to have up to 4 mega-[[byte]]s of main memory. | |
| − | + | All devices were attached to a separate [[UNIBUS]]; [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to MASSBUS controllers. | |
| + | |||
| + | The optional [[FP11-B Floating-Point Processor]] (full [[FP11 floating point]]), and up to four [[RH70 MASSBUS controller]]s plugged into the CPU's [[backplane]]. | ||
==Boards== | ==Boards== | ||
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* M8137 System Address Paths | * M8137 System Address Paths | ||
* M8138 System Status Registers | * M8138 System Status Registers | ||
| − | * M8140 System Descriptor | + | * M8140 System Descriptor amd Console Cables |
* M8141 UNIBUS Map | * M8141 UNIBUS Map | ||
* M8142 Cache Control | * M8142 Cache Control | ||
| − | * M8143 Address Memory | + | * M8143 Cache Address Memory |
| − | * M8144 Data Memory | + | * M8144 Cache Data Memory |
* M8145 Cache Data Paths | * M8145 Cache Data Paths | ||
| Line 29: | Line 31: | ||
* M8139 Timing Generator | * M8139 Timing Generator | ||
| − | The M8130 through M8139 boards are based on those of the | + | === Board sharing=== |
| + | |||
| + | The M8130 through M8139 boards are based on those of the KB11-A CPU of the -11/45; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc). | ||
| + | |||
| + | In fact, as reported (in the thread below), many of the boards are so similar that the M813x of the KB11-B can be used in place of the M810x of the KB11-A. Comparing an actual M8101 with an M8131, the [[etch]] of the former is given as "M8101B" and the latter is given as "M8101 C-P2" (although other M8131's are reported to use the M8101B etch). The [[trace]]s are mostly identical, but there are a few minor differences. | ||
==See also== | ==See also== | ||
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* [[KB11-C CPU]] | * [[KB11-C CPU]] | ||
| − | + | ==External links== | |
| + | |||
| + | * [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-KB11B-TM-001%20KB11-B%20Processor%20Manual%20(PDP-1170).pdf KB11-B Processor Manual (PDP-11/70)] (EK-KB11B-TM-001) | ||
| + | * [http://bitsavers.org/pdf/dec/pdp11/1170/1170_Engineering_Drawings_revB_1977.pdf KB11-B 16-Bit Processor Engineering Drawings (5/1977)] | ||
| + | * [https://forum.vcfed.org/index.php?threads/pdp-11-45-part-5.54005/post-656568 PDP 11/45, Part 5] | ||
| − | [[Category: | + | [[Category: PDP-11 UNIBUS Processors]] |
Latest revision as of 21:08, 2 July 2023
The KB11-B CPU is the earlier CPU for the PDP-11/70. It is heavily based on the PDP-11/45's KB11-A CPU; the -11/70 is basically an -11/45 with a cache, more main memory, and provision for high/speed I/O device controllers for MASSBUS devices.
Full PDP-11 Memory Management and the cache were standard on all KB11-B's. It used a special 32-bit wide memory bus, the Main Memory Bus, unique to the -11/70, for its bus to main memory; in addition to the speedup of doubling the width, this bus also allowed it to have up to 4 mega-bytes of main memory.
All devices were attached to a separate UNIBUS; DMA devices could gain access to the memory via a UNIBUS map which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to MASSBUS controllers.
The optional FP11-B Floating-Point Processor (full FP11 floating point), and up to four RH70 MASSBUS controllers plugged into the CPU's backplane.
Boards
The basic KB11-B consisted of fifteen hex boards:
- M8130 Data Paths
- M8131 General Registers and ALU Control
- M8132 Instruction Register Decode and Condition Codes
- M8133 ROM and ROM Control
- M8134 Processor Data and UNIBUS Registers
- M8135 Trap and Miscellaneous Control
- M8136 UNIBUS and Console Control
- M8137 System Address Paths
- M8138 System Status Registers
- M8140 System Descriptor amd Console Cables
- M8141 UNIBUS Map
- M8142 Cache Control
- M8143 Cache Address Memory
- M8144 Cache Data Memory
- M8145 Cache Data Paths
and a quad board:
- M8139 Timing Generator
Board sharing
The M8130 through M8139 boards are based on those of the KB11-A CPU of the -11/45; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc).
In fact, as reported (in the thread below), many of the boards are so similar that the M813x of the KB11-B can be used in place of the M810x of the KB11-A. Comparing an actual M8101 with an M8131, the etch of the former is given as "M8101B" and the latter is given as "M8101 C-P2" (although other M8131's are reported to use the M8101B etch). The traces are mostly identical, but there are a few minor differences.
