Difference between revisions of "LSI-11 CPUs"

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(Have a page for the pair)
 
(Does in fact work with Q18)
 
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The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], the first to use a [[microprocessor]] (the [[LSI-11 chip set]]). They used a new [[bus]], the [[QBUS]].
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The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]].
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They were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, the main [[asynchronous serial line|serial line]] is used as a operating console, using the [[QBUS CPU ODT|ODT functionality]].
  
 
The first [[LSI-11]] was a [[DEC card form factor|quad]] board (M7264) with additional functionality on-board. A later board, the [[LSI-11/2]], packaged just the CPU on a dual card.
 
The first [[LSI-11]] was a [[DEC card form factor|quad]] board (M7264) with additional functionality on-board. A later board, the [[LSI-11/2]], packaged just the CPU on a dual card.
  
Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11. The reason for the incompatability with Q18 memory is currently unknown.)
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==Limitations==
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Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]] (at location 0). The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT.
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Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 or Q18 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.<!--The reason for the incompatability with Q18 memory is currently unknown.-->)
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==Options==
  
 
There were CPU options were available for the LSI-11s: the [[KEV11-A floating point|KEV11-A]], for the [[PDP-11 Extended Instruction Set|EIS]]/[[FIS floating point|FIS]] instructions; the [[KEV11-B Extended Instruction Set|KEV11-B]] provides EIS without FIS; the [[KEV11-C Commercial Instruction Set|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but not the FIS).
 
There were CPU options were available for the LSI-11s: the [[KEV11-A floating point|KEV11-A]], for the [[PDP-11 Extended Instruction Set|EIS]]/[[FIS floating point|FIS]] instructions; the [[KEV11-B Extended Instruction Set|KEV11-B]] provides EIS without FIS; the [[KEV11-C Commercial Instruction Set|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but not the FIS).

Latest revision as of 20:36, 2 May 2020

The LSI-11 CPUs were DEC's first cost-reduced PDP-11 CPUs, using a microprocessor (the LSI-11 chip set). They also used a new bus, the QBUS.

They were the first PDP-11 models to not have a front panel to control them; instead, as a cost-reduction measure, the main serial line is used as a operating console, using the ODT functionality.

The first LSI-11 was a quad board (M7264) with additional functionality on-board. A later board, the LSI-11/2, packaged just the CPU on a dual card.

Limitations

Note that ODT will not function correctly in the LSI-11s unless there is main memory on the QBUS (at location 0). The reason for this restriction is unknown: the KDF11 CPUs and KDJ11 CPUs, which also use ODT, do not have this limitation; e.g. a system consisting only of a KDF11-A CPU and a serial console will run ODT.

Both LSI-11s are Q16 devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 backplane, they will only function with Q16 or Q18 main memory. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.)

Options

There were CPU options were available for the LSI-11s: the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).

They also supported the optional KUV11 Writeable Control Store.