Difference between revisions of "MLH-DH/LSI11 Multiple Channel Controller"
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The '''MLH-DH/LSI11 Multiple Channel Controller''' is a [[Direct Memory Access|DMA]] [[QBUS]] [[IMP interface]] produced by [[Advanced Computer Communications|ACC]] to allow a QBUS machine to connect to an [[ARPANET]] [[Interface Message Processor|IMP]]. | The '''MLH-DH/LSI11 Multiple Channel Controller''' is a [[Direct Memory Access|DMA]] [[QBUS]] [[IMP interface]] produced by [[Advanced Computer Communications|ACC]] to allow a QBUS machine to connect to an [[ARPANET]] [[Interface Message Processor|IMP]]. | ||
| − | It consists of 2 or more [[DEC card form factor|dual]] [[printed circuit board]]s (one which is the QBUS interface, the MICRO-11 [[device controller|controller]], joined to one or more [[ | + | It consists of 2 or more [[DEC card form factor|dual]] [[printed circuit board]]s (one which is the QBUS interface, the MICRO-11 [[device controller|controller]], joined to one or more [[1822 interface]] cards), connected together by a [[flat cable]] running to 40-pin [[Berg connector]] headers on the card ends. Level converters allow use as either a Local Host or Distant Host interface; a cable from a further 26-pin Berg connector header leads to the standard 1822 Amphenol connector, which will be mounted on the rear bulkhead. |
It was created by ACC under contract from [[SRI International|SRI]]. It is [[program compatible]] with ACC's earlier [[UNIBUS]] [[LH-DH/11 Local/Distant Host Controller]]. | It was created by ACC under contract from [[SRI International|SRI]]. It is [[program compatible]] with ACC's earlier [[UNIBUS]] [[LH-DH/11 Local/Distant Host Controller]]. | ||
| Line 98: | Line 98: | ||
* XQ/1822 Maintenance Manual | * XQ/1822 Maintenance Manual | ||
| + | ==See also== | ||
| + | |||
| + | * [[LH-DH/11 Local/Distant Host Controller|LH-DH/11]] | ||
<!--==External links== | <!--==External links== | ||
--> | --> | ||
| + | [[Category: 1822 Interfaces]] | ||
[[Category: QBUS Network Interfaces]] | [[Category: QBUS Network Interfaces]] | ||
Latest revision as of 16:35, 8 November 2021
The MLH-DH/LSI11 Multiple Channel Controller is a DMA QBUS IMP interface produced by ACC to allow a QBUS machine to connect to an ARPANET IMP.
It consists of 2 or more dual printed circuit boards (one which is the QBUS interface, the MICRO-11 controller, joined to one or more 1822 interface cards), connected together by a flat cable running to 40-pin Berg connector headers on the card ends. Level converters allow use as either a Local Host or Distant Host interface; a cable from a further 26-pin Berg connector header leads to the standard 1822 Amphenol connector, which will be mounted on the rear bulkhead.
It was created by ACC under contract from SRI. It is program compatible with ACC's earlier UNIBUS LH-DH/11 Local/Distant Host Controller.
Contents
- 1 Registers
- 1.1 0767600: Receive Control Status Register (RCSR)
- 1.2 0767602: Receive Data Buffer Register (RDBR)
- 1.3 0767604: Receive Current Address Register (RCAR)
- 1.4 0767606: Receive Word Count Register (RWCR)
- 1.5 0767610: Transmit Control Status Register (TCSR)
- 1.6 0767612: Transmit Data Buffer Register (TDBR)
- 1.7 0767614: Transmit Current Address Register (TCAR)
- 1.8 0767616: Transmit Word Count Register (TWCR)
- 2 Further reading
- 3 See also
Registers
| Register | Abbreviation | Address |
|---|---|---|
| Receive Control Status Register | RCSR | 0767600 |
| Receive Data Buffer Register | RDBR | 0767602 |
| Receive Current Address Register | RCAR | 0767604 |
| Receive Word Count Register | RWCR | 0767606 |
| Transmit Control Status Register | CSRO | 0767610 |
| Transmit Data Buffer Register | DBRO | 0767612 |
| Transmit Current Address Register | CWAO | 0767614 |
| Transmit Word Count Register | WCO | 0767616 |
0767600: Receive Control Status Register (RCSR)
| RERR | MTO | REOM | Unused | HRYO | IRYO | RYER | RBF | RRDY | RIEN | XBA16-17 | RCVEN | HRLY | RST | RGO | |
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
- RERR - Error Flag
- MTO - Non-Existent Memory
- REOM - End of Message
- HRYO - Host Ready
- IRYO - IMP Not Ready
- RYER - Receive Master Ready Error
- RBF - Input Data Buffer Full
- RRDY - Device Ready
- RIEN - Interrupt Enable
- RCVEN - Store Enable
- HRLY - Host Relay Control
- RST - Input Interface Reset
0767602: Receive Data Buffer Register (RDBR)
| Data15 <---> Data00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Read only register.
0767604: Receive Current Address Register (RCAR)
| CA15 <---> CA00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767606: Receive Word Count Register (RWCR)
| WC15 <---> WC00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767610: Transmit Control Status Register (TCSR)
| TERR | TMTO | Unused | RYER | TBE | TRDY | TIEN | XBA16-17 | BBAK | LBIT | RST | TGO | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
- TERR - Error Flag
- TMTO - Non-Existent Memory
- RYER - Transmit Master Ready Error
- TBE - Output Data Buffer Empty
- TRDY - Device Ready
- TIEN - Interrupt Enable
- BBAK - Bus-Back Mode
- LBIT - Enable Last Bit
- RST - Output Interface Reset
0767612: Transmit Data Buffer Register (TDBR)
| Data15 <---> Data00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Write only register.
0767614: Transmit Current Address Register (TCAR)
| CA15 <---> CA00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767616: Transmit Word Count Register (TWCR)
| WC15 <---> WC00 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Further reading
- MDMA Multichannel DMA Controller for LSI-11 Maintenance Manual
- XQ/1822 Maintenance Manual
