Difference between revisions of "MSV11-L MOS Random-Access Memory"

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[[Image:MSV11-L.jpg|thumb|250px|right|MSV11-L card]]
 
[[Image:MSV11-L.jpg|thumb|250px|right|MSV11-L card]]
  
The '''MSV11-L''' (M8059) is a [[DEC card form factor|dual]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAMs  [[integrated circuit|chips]], the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)
+
The '''MSV11-L''' is a [[QBUS]] [[DEC card form factor|dual]]-height [[Dynamic RAM|DRAM]] [[main memory]] card ('''M8059'''). It can be configured as either a [[QBUS#Variable address size|Q18]] card, or a Q22 card<!--; it reportedly supports QBUS block mode-->; it supports [[byte]] [[parity]].
  
The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It can be configured as either a [[QBUS#Variable address size|Q18]] card, or a Q22 card<!--; it reportedly supports QBUS block mode-->.
+
The memory is arranged as 2 banks, each 16 data bits (one [[PDP-11]] [[word]]) wide. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAM [[integrated circuit|chips]], the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)
 +
 
 +
[[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]]s are 560-590 nsec for reads, 605-635 nsec for writes, and 1140-1170 nsec for read/write (DATIO) cycles. [[Memory refresh]] time (and conflict delay) is 650-685 nsec.
 +
 
 +
==Control and Status Register==
 +
 
 +
Each board has a single [[register]], a Control and Status Register, which can be configured in the range 17772100-17772116 (below). In the register contents, all the bits can be read and written by [[software]]; all, other than 'Error Address', are cleared by power up and QBUS INIT. Bits which can only be modified by the [[CPU]] are shown in normal font, and those which can also be set by the board [[hardware]] in ''italics''.
 +
{{16bit-header}}
 +
| ''Parity Error'' || Extended Error Address Enable || colspan=2 | Unused || colspan=7 | ''Error Address'' || colspan=2 | Unused || Write Wrong Parity || Unused || Parity Error Enable
 +
{{16bitoctal-bitout}}
 +
 
 +
The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 17 through 11); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5 - bits 11-9 of the register will still hold address bits 17-15).
  
 
==Configuration==
 
==Configuration==
  
The card is configured by [[jumper]]s on [[wire-wrap]] posts; it is possible to set:
+
[[Image:MSV11-LDiag.jpg|250px|thumb|right|M8059 jumper locations]]
 +
 
 +
The card is configured by [[wire-wrap]] [[jumper]]s between posts; it is possible to set:
 +
 
 
* the starting address;
 
* the starting address;
 
* the size (256KB or 128KB);
 
* the size (256KB or 128KB);
* the CSR address;
+
* the CSR register; and its address, if so;
 
* parity enable;
 
* parity enable;
 
* parity error action;
 
* parity error action;
 
* enable wrong parity;
 
* enable wrong parity;
* bank disable.
+
* bank disable
<!-- {| class="wikitable"
+
 
! S1 || S2 || Staring Address
+
Since the manual (below) is not available online, here are the jumper details:
 +
 
 +
{| class="wikitable"
 +
! Function !! State !! Jumper
 
|-
 
|-
| OFF || OFF || 00000000 (0 MB)
+
| rowspan="2" | Parity || Enable || 9 to 10
 
|-
 
|-
| OFF || ON ||  04000000 (1 MB)
+
| Disable || 11 to 10
 
|-
 
|-
| ON || OFF || 10000000 (2 MB)
+
| rowspan="2" | Allow clearing 'error enable' || Allow || 20 to 19
 
|-
 
|-
| ON || ON || 14000000 (3 MB)
+
| Disallow || 18 to 19
 +
|-
 +
| rowspan="2" | Parity report || BDAL 16 || 3 to 2
 +
|-
 +
| BDAL 16 and 17 || 1 to 2
 +
|-
 +
| rowspan="2" | Write wrong parity || Disable || 8 to 7
 +
|-
 +
| Enable || 6 to 7
 +
|-
 +
| rowspan="2" | CSR || Disable || J to H
 +
|-
 +
| Enable || F to H
 +
|-
 +
| rowspan="2" | I/O page size || 2KW || 29 to 28
 +
|-
 +
| 4KW || 27 to 28
 +
|-
 +
| rowspan="2" | Board size || Half || 32 to 33
 +
|-
 +
| Full || 34 to 33
 +
|-
 +
| rowspan="2" | Which half || Remove lower || 17 to 16
 +
|-
 +
| Normal or Remove upper || 15 to 16
 +
|-
 +
| rowspan="2" | Q18 or Q22 || Q18 || R to T ''out''
 +
|-
 +
| Q22 || R to T in
 +
|}
 +
 
 +
===Register address===
 +
 
 +
Jumper from pin 'E' to the listed pins:
 +
 
 +
{| class="wikitable"
 +
! C !! B !! A !! CSR Address
 +
|-
 +
| Out || Out || Out || 17772100
 +
|-
 +
| Out || Out || In || 17772102
 +
|-
 +
| Out || In || Out || 17772104
 +
|-
 +
| Out || In || In || 17772106
 +
|-
 +
| In || Out || Out || 17772110
 +
|-
 +
| In || Out || In || 17772112
 +
|-
 +
| In || In || Out || 17772114
 +
|-
 +
| In || In || In || 17772116
 
|}
 
|}
  
==Control Register==
+
(Addresses are given in Q22 form; for Q18 operation, delete the high '17'.)
Each board has a single control [[register]], which can be configured in the range 17772100-17772136.
+
 
 +
===Starting address (high)===
 +
 
 +
Jumper from pin 'K' to the listed pins:
 +
 
 
{| class="wikitable"
 
{| class="wikitable"
! S5 !! S6 !! S7 !! S8 !! CSR Address
+
! P || N || M || L || Staring Address
 
|-
 
|-
| ON || ON || ON || ON || 17772100
+
| Out || Out || Out || Out || 00000000
 
|-
 
|-
| ON || ON || ON || OFF || 17772102
+
| Out || Out || Out || In || 01000000
 
|-
 
|-
| ON || ON || OFF || ON || 17772104
+
| Out || Out || In || Out || 02000000
 
|-
 
|-
| ON || ON || OFF || OFF || 17772106
+
| Out || Out || In|| In || 03000000
 
|-
 
|-
| ON || OFF || ON || ON || 17772110
+
| Out || In || Out || Out || 04000000 (1 MB)
 
|-
 
|-
| ON || OFF || ON || OFF || 17772112
+
| Out || In || Out || In || 05000000
 
|-
 
|-
| ON || OFF || OFF || ON || 17772114
+
| Out || In || In || Out || 06000000
 
|-
 
|-
| ON || OFF || OFF || OFF || 17772116
+
| Out || In || In || In || 07000000
 
|-
 
|-
| OFF || ON || ON || ON || 17772120
+
| In || Out || Out || Out || 10000000 (2 MB)
 
|-
 
|-
| OFF || ON || ON || OFF || 17772122
+
| In || Out || Out || In || 11000000
 
|-
 
|-
| OFF || ON || OFF || ON || 17772124
+
| In || Out || In || Out || 12000000
 
|-
 
|-
| OFF || ON || OFF || OFF || 17772126
+
| In || Out || In || In || 13000000
 
|-
 
|-
| OFF || OFF || ON || ON || 17772130
+
| In || In || Out || Out || 14000000 (3 MB)
 
|-
 
|-
| OFF || OFF || ON || OFF || 17772132
+
| In || In || Out || In || 15000000
 
|-
 
|-
| OFF || OFF || OFF || ON || 17772134
+
| In || In || In || Out || 16000000
 
|-
 
|-
| OFF || OFF || OFF || OFF || 17772136
+
| In || In || In || In || 17000000
 
|}
 
|}
In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
 
{{16bit-header}}
 
| ''Parity Error'' || Extended Error Address Enable || colspan=2 | Reserved || colspan=7 | ''Error Address'' || colspan=2 | Reserved || Write Wrong Parity || Reserved || Parity Error Enable
 
{{16bitoctal-bitout}}
 
The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit; when it holds the low address ('Extended Error Address Enable' is 0), it holds address bits 11 through 17; when it holds the high address ('Extended Error Address Enable' is 1), it holds bits 21 through 18 - bits 11-9 of the register are unused.
 
  
==Technical information==
+
===Starting address (low)===
 +
 
 +
Jumper from pin 'U' to the listed pins:
 +
 
 +
{| class="wikitable"
 +
! Z || Y || X || W || V || Staring Address
 +
|-
 +
| Out || Out || Out || Out || Out || 000000
 +
|-
 +
| Out || Out || Out || Out || In || 020000
 +
|-
 +
| Out || Out || Out || In || Out || 040000
 +
|-
 +
| Out || Out || Out || In || In || 060000
 +
|-
 +
| Out || Out || In || Out || Out || 100000
 +
|-
 +
| Out || Out || In || Out || In || 120000
 +
|-
 +
| Out || Out || In || In || Out || 140000
 +
|-
 +
| Out || Out || In || In || In || 160000
 +
|-
 +
| Out || In || Out || Out || Out || 200000
 +
|-
 +
| Out || In || Out || Out || In || 220000
 +
|-
 +
| Out || In || Out || In || Out || 240000
 +
|-
 +
| Out || In || Out || In || In || 260000
 +
|-
 +
| Out || In || In || Out || Out || 300000
 +
|-
 +
| Out || In || In || Out || In || 320000
 +
|-
 +
| Out || In || In || In || Out || 340000
 +
|-
 +
| Out || In || In || In || In || 360000
 +
|-
 +
| In || Out || Out || Out || Out || 400000
 +
|-
 +
| In || Out || Out || Out || In || 420000
 +
|-
 +
| In || Out || Out || In || Out || 440000
 +
|-
 +
| In || Out || Out || In || In || 460000
 +
|-
 +
| In || Out || In || Out || Out || 500000
 +
|-
 +
| In || Out || In || Out || In || 520000
 +
|-
 +
| In || Out || In || In || Out || 540000
 +
|-
 +
| In || Out || In || In || In || 560000
 +
|-
 +
| In || In || Out || Out || Out || 600000
 +
|-
 +
| In || In || Out || Out || In || 620000
 +
|-
 +
| In || In || Out || In || Out || 640000
 +
|-
 +
| In || In || Out || In || In || 660000
 +
|-
 +
| In || In || In || Out || Out || 700000
 +
|-
 +
| In || In || In || Out || In || 720000
 +
|-
 +
| In || In || In || In || Out || 740000
 +
|-
 +
| In || In || In || In || In || 760000
 +
|}
  
As far as is known, there are no copies of the engineering drawings extant for the MSV11-M.<!--However, some technical information, enough to [[repairing un-documented MOS memory boards|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.
+
<!-- ==Technical information==
As described above, each board has 2 banks in the array of DRAM chips; with 256K chips, each bank is thus 512KB. (Note that when writing data, the MSV11-R sends a 'write' [[signal]] to ''all'' the banks, and selects the one to ''actually'' use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)
 
 
-->
 
-->
<!-- ''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.
+
==Further reading==
The following 256K DRAM chips have been observed to be used: MB81256-15 (Fujitsu). M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments)
 
Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage. -->
 
  
==Further reading==
+
* ''MSV11-L User Guide'', EK-MSV0L-UG (not available online)
  
* ''MSV11-L User Guide'', EK-MSV0L-UG
+
==External links==
* ''MSV11-L Field Maintenance Printset'' (MP-01238 (M)
 
  
{{PDP-11}}
+
* ''MSV11-L Field Maintenance Printset'' (MP-01238)
 +
** [https://www.mainecoon.com/classiccmp/MSV11-L/MSV11-L%20FMPS%20MP01238%20(M8059)%20part-1.tif part 1]
 +
** [https://www.mainecoon.com/classiccmp/MSV11-L/MSV11-L%20FMPS%20MP01238%20(M8059)%20part-2.tif part 2]
  
 
[[Category: QBUS Memories]]
 
[[Category: QBUS Memories]]

Latest revision as of 13:10, 22 September 2022

MSV11-L card

The MSV11-L is a QBUS dual-height DRAM main memory card (M8059). It can be configured as either a Q18 card, or a Q22 card; it supports byte parity.

The memory is arranged as 2 banks, each 16 data bits (one PDP-11 word) wide. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAM chips, the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)

Access time is 210-230 nsec for reads, and 90-120 nsec for writes; cycle times are 560-590 nsec for reads, 605-635 nsec for writes, and 1140-1170 nsec for read/write (DATIO) cycles. Memory refresh time (and conflict delay) is 650-685 nsec.

Control and Status Register

Each board has a single register, a Control and Status Register, which can be configured in the range 17772100-17772116 (below). In the register contents, all the bits can be read and written by software; all, other than 'Error Address', are cleared by power up and QBUS INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the board hardware in italics.

Parity Error Extended Error Address Enable Unused Error Address Unused Write Wrong Parity Unused Parity Error Enable
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 17 through 11); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5 - bits 11-9 of the register will still hold address bits 17-15).

Configuration

M8059 jumper locations

The card is configured by wire-wrap jumpers between posts; it is possible to set:

  • the starting address;
  • the size (256KB or 128KB);
  • the CSR register; and its address, if so;
  • parity enable;
  • parity error action;
  • enable wrong parity;
  • bank disable

Since the manual (below) is not available online, here are the jumper details:

Function State Jumper
Parity Enable 9 to 10
Disable 11 to 10
Allow clearing 'error enable' Allow 20 to 19
Disallow 18 to 19
Parity report BDAL 16 3 to 2
BDAL 16 and 17 1 to 2
Write wrong parity Disable 8 to 7
Enable 6 to 7
CSR Disable J to H
Enable F to H
I/O page size 2KW 29 to 28
4KW 27 to 28
Board size Half 32 to 33
Full 34 to 33
Which half Remove lower 17 to 16
Normal or Remove upper 15 to 16
Q18 or Q22 Q18 R to T out
Q22 R to T in

Register address

Jumper from pin 'E' to the listed pins:

C B A CSR Address
Out Out Out 17772100
Out Out In 17772102
Out In Out 17772104
Out In In 17772106
In Out Out 17772110
In Out In 17772112
In In Out 17772114
In In In 17772116

(Addresses are given in Q22 form; for Q18 operation, delete the high '17'.)

Starting address (high)

Jumper from pin 'K' to the listed pins:

P N M L Staring Address
Out Out Out Out 00000000
Out Out Out In 01000000
Out Out In Out 02000000
Out Out In In 03000000
Out In Out Out 04000000 (1 MB)
Out In Out In 05000000
Out In In Out 06000000
Out In In In 07000000
In Out Out Out 10000000 (2 MB)
In Out Out In 11000000
In Out In Out 12000000
In Out In In 13000000
In In Out Out 14000000 (3 MB)
In In Out In 15000000
In In In Out 16000000
In In In In 17000000

Starting address (low)

Jumper from pin 'U' to the listed pins:

Z Y X W V Staring Address
Out Out Out Out Out 000000
Out Out Out Out In 020000
Out Out Out In Out 040000
Out Out Out In In 060000
Out Out In Out Out 100000
Out Out In Out In 120000
Out Out In In Out 140000
Out Out In In In 160000
Out In Out Out Out 200000
Out In Out Out In 220000
Out In Out In Out 240000
Out In Out In In 260000
Out In In Out Out 300000
Out In In Out In 320000
Out In In In Out 340000
Out In In In In 360000
In Out Out Out Out 400000
In Out Out Out In 420000
In Out Out In Out 440000
In Out Out In In 460000
In Out In Out Out 500000
In Out In Out In 520000
In Out In In Out 540000
In Out In In In 560000
In In Out Out Out 600000
In In Out Out In 620000
In In Out In Out 640000
In In Out In In 660000
In In In Out Out 700000
In In In Out In 720000
In In In In Out 740000
In In In In In 760000

Further reading

  • MSV11-L User Guide, EK-MSV0L-UG (not available online)

External links

  • MSV11-L Field Maintenance Printset (MP-01238)