Difference between revisions of "Maxc"

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The [[main memory]] was built out of then-novel [[Dynamic RAM|DRAM]] [[integrated circuit|chips]] from [[Intel]], the new [[Intel 1103]] 1Kx1 chip. It used [[error-correcting code|ECC]] to produce reliable memory; with a [[word]] length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance.
 
The [[main memory]] was built out of then-novel [[Dynamic RAM|DRAM]] [[integrated circuit|chips]] from [[Intel]], the new [[Intel 1103]] 1Kx1 chip. It used [[error-correcting code|ECC]] to produce reliable memory; with a [[word]] length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance.
  
They ran the [[TENEX]] [[operating system]]; to do this, Maxc implemented [[virtual memory]] mechanisms comparable to those added to the [[KA10]] by [[Bolt, Beranek, and Newman|BBN]], including a 102x18 bit mapping memory.
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They ran the [[TENEX]] [[operating system]]; to do this, Maxc implemented [[virtual memory]] mechanisms comparable to those added to the [[KA10]] by [[Bolt, Beranek, and Newman|BBN]], including a 1024x18 bit mapping memory.
  
 
Maxcl built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977.
 
Maxcl built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977.
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** [http://www.bitsavers.org/pdf/xerox/maxc/MAXC_Operations_May74.pdf Maxc Operations]
 
** [http://www.bitsavers.org/pdf/xerox/maxc/MAXC_Operations_May74.pdf Maxc Operations]
 
** [http://www.bitsavers.org/pdf/xerox/maxc/MAXC_8.2_Spec.pdf The MAXC Microprocessor]
 
** [http://www.bitsavers.org/pdf/xerox/maxc/MAXC_8.2_Spec.pdf The MAXC Microprocessor]
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* [http://www.softwarepreservation.org/projects/LISP/interlisp-d/Deutsch-3IJCAI.pdf A LISP Machine with Very Compact Programs], L. Peter Deutsch, 1973.
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* [https://github.com/PDP-10/maxc/tree/master/monitor Maxc monitor sources (and other files related to PUP)]
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* [https://xeroxalto.computerhistory.org/_cd8_/pup/.index.html Alto directory with some Maxc files], i.e. .MAC, .SAV, .REL, .UNV.
  
[[Category: PDP-10s]]
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[[Category: PDP-10 Systems]]
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[[Category: Xerox Mainframes]]

Latest revision as of 01:20, 28 May 2022

Xerox Maxc

Maxc1 and Maxc2 (often capitalized MAXC) were a pair of PDP-10 clones made at Xerox PARC, after the Xerox corporate level objected to the acquisition of machines from outside the company, instead of from Xerox's subsidiary, Xerox Data Systems - Scientific Data Systems before it was acquired by Xerox. (They chose the PDP-10 as they wanted to be able to run INTERLISP.)

They were microcoded machines, using an 72-bit microinstruction. They contained 2K words of microcode, and microinstructions executed in 200 nsec (Maxc1); 4K words, at 150 nsec (Maxc2). The hardware supported up to 16 levels of subroutine calls in the microcode. This capability was used to support bulk data transfers (from disk mass storage); a technique which was later used in the Alto.

In addition to a PDP-10-compatible mode, MAXC microcode also implemented a Byte Lisp mode with 9-bit instructions specially tailored for LISP. The INTERLISP compiler and runtime has support for this instruction set under a MAXC condition, and the MAXC monitor has special JSYS calls to facilitate Byte Lisp code.

A front end (a Data General Nova on Maxc1, and an Alto on Maxc2) was used to load and debug the microcode; all the input/output peripherals other than the disks were also connected to the front end.

The main memory was built out of then-novel DRAM chips from Intel, the new Intel 1103 1Kx1 chip. It used ECC to produce reliable memory; with a word length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance.

They ran the TENEX operating system; to do this, Maxc implemented virtual memory mechanisms comparable to those added to the KA10 by BBN, including a 1024x18 bit mapping memory.

Maxcl built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977.

Further reading

  • Michael A. Hiltzik, Dealers of Lightning: Xerox PARC and the Dawn of the Computer Age, HarperBusiness, New York, 1999 - pp. 99-116

External links