Difference between revisions of "PDP-8/I"

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{{Infobox Machine  
 
{{Infobox Machine  
 
| name = PDP-8/I
 
| name = PDP-8/I
| image = PDP-8'I ComputerCabinettGöttingen.jpg
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| image = PDP-8'I FrontPanel.jpg
| caption = PDP-8/S in the Göttingen Computer Club in Göttingen, Germany
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| caption = PDP-8/I front panel
 
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| ram = Maximum of 32 kwords in eight 4 kword banks
 
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It could perform an addition to the [[accumulator]] in 3.0 μseconds, and a 12 by 12 bit multiplication with 24 bit result in 6.0 μseconds, using the math extension hardware.
 
It could perform an addition to the [[accumulator]] in 3.0 μseconds, and a 12 by 12 bit multiplication with 24 bit result in 6.0 μseconds, using the math extension hardware.
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==Images==
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[[Image:PDP-8'I HoppeLighted.jpg|left|thumb|400px|PDP-8/I of the Göttingen Computer Club in Göttingen, Germany]]
  
 
{{Nav PDP-8}}
 
{{Nav PDP-8}}
  
 
[[Category: PDP-8s]]
 
[[Category: PDP-8s]]

Latest revision as of 21:15, 8 January 2021


PDP-8/I
PDP-8'I FrontPanel.jpg
PDP-8/I front panel
Year Introduced: 1968
Form Factor: minicomputer
Word Size: 12
Logic Type: TTL
Design Type: clocked random logic
Clock Speed: 333KHz
Memory Speed: 1.5 μseconds
Physical Address Size: 32KW (requires optional MC8/I)
Virtual Address Size: 4KW
Memory Management: bank selection, CPU mode
Bus Architecture: negative I/O bus
Operating System: TSS/8. Disk Monitor System
Predecessor(s): PDP-8
Successor(s): PDP-8/E


The PDP-8/I was introduced in 1968 as the successor to the PDP-8. It was constructed out of TTL ICs on M-class FLIP CHIPs.

Options included:

  • KA8/IB Positive I/O Bus Interface, to allow use of newer PDP-8 devices
  • MC8/I Memory Extension Control, which was needed to support more than 4K words of memory
  • MP8/I Memory Parity
  • KE8/I Extended Arithmetic Element, which supported hardware integer multiplication and division, one-bit double-word shifts, and normalization
  • KT8/I Time Sharing Hardware Modification, which allowed the computer to operate in either Executive Mode or User Mode

It could perform an addition to the accumulator in 3.0 μseconds, and a 12 by 12 bit multiplication with 24 bit result in 6.0 μseconds, using the math extension hardware.

Images

PDP-8/I of the Göttingen Computer Club in Göttingen, Germany