RH70 MASSBUS controller
One the -11/70 side, it contains connections to both the -11/70's main memory and cache (for data reads and writes from the device), as well as to the UNIBUS (for interrupts, and access to the device's registers by the CPU).
The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memory location which is stored in the cache invalidates that cache entry.
Each RH70 (up to a maximum of 4) consisted of a special pre-wired 4-slot section of the CPU's backplane, into which plugged a number of cards:
- M8150 - MDP - Data buffer and parity
- M8151 - CST - Control and Status
- M8152 - AWR - Address and Word Count registers
- M8152 - BCT - bus control
Three dual-height M5904 MASSBUS transceiver modules.
The RH70 contains 6 registers, plus a share of a seventh; they are
- RHCS1 - Control and Status 1 (shared)
- RHWC - Word Count
- RHBA - Bus Address
- RHBAE - Bus Address Extension
- RHCS2 - Control and Status 2
- RHCS3 - Control and Status 3
- RHDB - Data Buffer (for maintenance)
As is standard for the MASSBUS, all the other device registers are in the device.