Difference between revisions of "RK11-C disk controller"

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* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/unibus/RK11-C_manual1971.pdf RK11-C manual, 1971]
* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/unibus/RK11-C_manual1971.pdf RK11-C manual, 1971]
* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/unibus/RK11-C_schemFeb1971.pdf RK11-C schematics, February 1971]
* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/unibus/RK11-C_schemFeb1971.pdf RK11-C schematics, February 1971]
* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/RK11-C-DB_EngrDrws_Dec72.pdf RK11-C-DB Double Buffer Disk Control Engineering Drawings, December 1972]
[[Category:UNIBUS Storage Controllers]]
[[Category:UNIBUS Storage Controllers]]

Revision as of 05:38, 2 December 2020

The RK11-C is the earliest known version of the RK11 disk controller. (Nothing is known of the -A and -B, if they ever existed as products, although see here for more about the RK11-C's predecessor.)

Like many of the earlier large peripheral controllers for the PDP-11, it was a large custom wire-wrapped backplane which bolted into the front or back of a 19 inch rack, such as an H960; into it plugged about 40 small M-Series FLIP CHIPs.

The backplane is wired for connection to a standard DEC indicator panel, but no inlay for such has even been sighted, although the RK11-C Engineering Drawings allow one to work out exactly what such an inlay would have looked like. It does however appear than the earlier version did have such an indicator panel.

Double Buffered RK11-C

RK11-C-DB data paths

There is also a rare variant of the RK11-C, the 'Double Buffer' RK11-C. It adds two 16-bit buffer registers (ABUF and BBUF), which are chained in an alternate data path between the UNIBUS and RKDB buffer register.

The motivation is not explicitly known (no documentation other than the engineering drawings is now extant), but it likely prevented under-run errors when there was considerable competing UNIBUS DMA traffic.

Engineering drawings

The engineering drawings for the Double Buffer RK11-C are very similar to those of the standard RK11-C. The differences are listed below.

(The engineering drawings available online for the original RK11-C have slightly different numbering for some pages, due to a change involving page 18, 'Disk Cable and Termination'. The Double Buffer set includes that page, but numbered it 21. The re-numbering of that first drawing from 18 to 21 caused the prints numbered from 19 to 21 in the original RK11-C set to be numbered one lower in the Double Buffer set; e.g. 'RKDB Data Paths' was 21 in the original RK11-C set, and is 20 in the Double Buffer set, and 'Bus "D" Drvrs and Rcvrs' changed from 19 to 18.)

New prints:

  • 24 - DSB/Bus -> ABuf Controls
  • 25 - ABuf/BBug Reg
  • 26 - Interbuffer Transfer Control
  • 27 - Buffer Control

Major changes:

  • 10 - RKDB and Control
  • 11B - Reg Sel, NPR & Int Control

Minor changes:

  • 13 - Adder Control (Adder Control #2 flop set input logic)
  • 15 - RKBA - RKWC - RKMR (logic lower left corner)
  • 16 - Errors (logic center driving DLT flop)
  • 17 - Cable Drivers (hand-written gate lower left)
  • 20 - RKDB Data Paths (replace 'BUS D' with 'BBUF' on all data bits)

Module count table

The following table gives a listing of the FLIP CHIPs used in the RK11-C and the Double-Buffered RK11-C. (Drawn from module utilization drawings, confirmed in module count charts.)

Single height boards:

Type RK11-C Double-Buffered Function
G736 1 1 Jumper
G740 1 1 Disk selection
M002 1 3 15 Loads
M105 1 1 Address selector
M111 2 5 Inverter
M112 5 7 NOR gate
M113 7 10 10 x 2-Input NAND gates
M115 3 4 8 x 3-Input NAND gates
M116 3 3 6 x 4-Input NOR gates
M117 3 4 6 x 4-Input NAND gates
M119 2 2 3 x 8-Input NAND gates
M121 3 3 AND/NOR gates
M141 2 2 NAND/NOR gates
M149 10 12 9 x 2-NAND wired OR matrix
M161 1 1 Binary to octal/decimal decoder
M163 1 1 Dual binary to decimal decoder
M203 4 4 8 x SR flip-flops
M205 3 4 5 x 'D' flip-flops
M207 1 1 J-K Flip-flops (3-3 configuration)
M208 2 6 8-bit buffer shift register
M214 3 3 6-bit register
M216 5 5 6 x flip-flops
M236 1 1 12-bit binary up/down counter
M238 1 1 Synchronous 4-bit up/down counter
M239 2 2 3 x 4-bit up/down counter/register
M304 3 5 One shot delay
M307 3 3 Integrating one shot
M405 1 1 Crystal clock
M606 0 2 Pulse generator
M611 1 1 High speed power inverter
M617 1 1 6 x 4-input NAND buffers
M623 3 3 Bus driver
M782 1 1 Interrupt control
M784 3 3 UNIBUS receivers
M796 1 1 UNIBUS master control
M797 1 1 Register select
M798 1 1 UNIBUS drivers

Double height boards:

  • M795 - Word Count and Current Memory Address

Module Utilization chart

The following table gives the FLIP CHIP locations in the backplane for the RK11-C and the Double-Buffered RK11-C (added FLIP CHIPs for the latter are in italics). The Flip Chip module utilization chart is as follows (* = Connector):

Slot A B C D
1 UNIBUS in M606 M113
2 UNIBUS out M115 M002
3 M149 M149 M208 M208
4 M111 M002 M205 M113
5 M105 M784 M208 M208
6 M782 M796 M304 M304
7 M795 M606 M112
8 M784 M784 M112 M111
9 M117 M111 M623 M307
10 Disk bus 2* M623 M307
11 M113 M623 M307
12 Disk bus 1* M207 M163
13 M798 G736 G740 M405
14 M149 M149 M116 M161
15 M149 M149 M304 M119
16 M149 M149 M113 M113
17 M239 M238 M216 M141
18 M239 M214 M115 M115
19 M214 M214 M121 M112
20 M208 M208 M111 M111
21 M203 M203 M112 M112
22 M149 M149 M205 M117
23 M149 M149 M203 M203
24 M121 M002 M116 M115
25 M216 M797 M611 M617
26 M141 M119 M113 M304
27 M304 M112 M112 M113
28 M236 M121 M216 M216
29 M205 M117 M117
30 W130* M113 M113
31 6775* M113 M205
32 6775* M116 M216

W130 = Maintenance board (optional)
6775 = Cable to indicator panel