Difference between revisions of "S-1 supercomputer"
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| − | The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all connected through a [[crossbar]] switch | + | The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all connected through a [[crossbar]] switch. |
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| + | Each [[CPU|processor]] had a [[cache]], but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and would have to request that the other processor flush its cache of that location. | ||
Five generations was planned, but only two were built the Mark I, and the Mark IIA. Both were [[wire-wrap]]ped; the Mark IIA was implemented in [[emitter-coupled logic|ECL]]. | Five generations was planned, but only two were built the Mark I, and the Mark IIA. Both were [[wire-wrap]]ped; the Mark IIA was implemented in [[emitter-coupled logic|ECL]]. | ||
| − | [[Common Lisp]] got many number crunching features from S-1 Lisp. | + | The architecture was inspired by the [[PDP-10]]; among other things the [[word]] size was 36 bits. [[Common Lisp]] got many number crunching features from S-1 Lisp. |
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* [http://www-forum.stanford.edu/wiki/index.php/S-1_project S-1 project] | * [http://www-forum.stanford.edu/wiki/index.php/S-1_project S-1 project] | ||
* [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1.html The Lawrence Livermore Laboratory S-1 project and Stanford University] | * [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1.html The Lawrence Livermore Laboratory S-1 project and Stanford University] | ||
| + | ** [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1/hardware.html Photographs of the S-1 computers] | ||
| + | ** [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1/CHM.html Photographs of the S-1 Mark I at the CHM warehouse] | ||
* [https://people.computing.clemson.edu/~mark/s1.html S-1 Supercomputer (1975-1988)] | * [https://people.computing.clemson.edu/~mark/s1.html S-1 Supercomputer (1975-1988)] | ||
[[Category: Mainframes]] | [[Category: Mainframes]] | ||
Revision as of 06:20, 29 January 2023
The S-1 was a supercomputer architecture jointly developed by Stanford University and Lawrence Livermore National Laboratory. It was MIMD multi-processor using shared memory, all connected through a crossbar switch.
Each processor had a cache, but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and would have to request that the other processor flush its cache of that location.
Five generations was planned, but only two were built the Mark I, and the Mark IIA. Both were wire-wrapped; the Mark IIA was implemented in ECL.
The architecture was inspired by the PDP-10; among other things the word size was 36 bits. Common Lisp got many number crunching features from S-1 Lisp.
External links
- S-1 Architecture Manual (STAN-CS-79-715)
- The S-1 Project - 1979 Annual Report: Volume I - Architecture
- The S-1 Project - 1979 Annual Report: Volume II - Hardware
- The S-1 Project - 1979 Annual Report: Volume III - Software
- The Amber Operating System
- S-1 project
- The Lawrence Livermore Laboratory S-1 project and Stanford University
- S-1 Supercomputer (1975-1988)
