Difference between revisions of "Small Peripheral Controller"

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'''Small Peripheral Controller''' or '''SPC''' was [[DEC]]'s name for an I/O board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s. It was a [[DEC card form factor|quad]] slot, occupying rows C-F in a hex slot, and could hold any kind of device.
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'''Small Peripheral Controller''' or '''SPC''' was [[DEC]]'s name for a board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s into which small [[device controller]]s, etc, could be plugged. It was a [[DEC card form factor|quad]]-high slot, occupying [[DEC edge connector contact identification|rows C-F]] in a hex slot.
  
It was originally conceived to hold a dual device-specific card, along with single-height M105 Address Selector and M782 (later M7820 and M7821 revisions) Interrupt Control [[FLIP CHIP]]s. The appropriate UNIBUS signal lines (address, data, etc) were thus wired to the appropriate rows/pins in SPC slots. It soon became more cost-effective to fabricate an entire device on a single quad card, but the pinout was retained.
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It was originally conceived to hold a dual-height device-specific card, along with single-height [[M105 Address Selector]] and [[M782 Interrupt Control]] [[FLIP CHIP]]s (later, the M7820 and M7821 revisions). (Among the dual-width controllers which did this were the [[KL11 asynchronous serial line interface‎|KL11]] (M780), the [[PC11 High-Speed Paper-Tape Reader/Punch Control|PC11]] (M781), the [[DR11-A parallel interface|DR11-A]] (M786), and the [[CR11 Controller|CR11]] (M829).)
  
SPC slots were wired to bring all 4 UNIBUS grant lines through the device; the board generally had a header which routed the grant (and matching request) line for the desired priority level to the on-board interrupt circuity, and passed the other grant lines through. The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot. Un-occupied slots needed to have a grant continuity card installed.
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The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins were wired to allow the necessary communication between the cards, without requiring cables between them.
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It soon became more cost-effective to fabricate an entire device on a single quad card, but the pinout was retained. (For the pinout of an SPC slot, see [[UNIBUS#Pinout|here]].)
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==Grants==
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SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request and Grant|NPG]]) and D (for BGx).
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The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed.
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The NPG grant line generally had a [[jumper]] on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a [[DMA]] device was plugged into that slot, or installed if one was removed; alternatively, a [[G7273 grant continuity card]] could be installed.
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==SPC Extensions==
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On some systems, some SPC pins were recycled for other purposes.
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In the [[PDP-11/04]] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
  
 
==See Also==
 
==See Also==
  
* [[Modified UNIBUS]]
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* [[Modified UNIBUS Device]]
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[[Category: UNIBUS]]

Revision as of 17:18, 17 November 2021

Small Peripheral Controller or SPC was DEC's name for a board slot in the backplanes of UNIBUS PDP-11s into which small device controllers, etc, could be plugged. It was a quad-high slot, occupying rows C-F in a hex slot.

It was originally conceived to hold a dual-height device-specific card, along with single-height M105 Address Selector and M782 Interrupt Control FLIP CHIPs (later, the M7820 and M7821 revisions). (Among the dual-width controllers which did this were the KL11 (M780), the PC11 (M781), the DR11-A (M786), and the CR11 (M829).)

The appropriate UNIBUS signal lines (address, data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins were wired to allow the necessary communication between the cards, without requiring cables between them.

It soon became more cost-effective to fabricate an entire device on a single quad card, but the pinout was retained. (For the pinout of an SPC slot, see here.)

Grants

SPC slots were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx).

The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the interrupt circuitry, and passed the other grant lines through. Un-occupied slots needed to have a G727 installed.

The NPG grant line generally had a jumper on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a DMA device was plugged into that slot, or installed if one was removed; alternatively, a G7273 grant continuity card could be installed.

SPC Extensions

On some systems, some SPC pins were recycled for other purposes.

In the PDP-11/04 and PDP-11/34, on the DD11-P backplane which holds the CPU card(s), along with the KY11-LB Programmer's Console (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.

See Also