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• MM11-E and MM1-F core memories
  ...''MM11-F core memories''' were [[UNIBUS]] [[main memory]] units; the first UNIBUS memories produced by [[Digital Equipment Corporation|DEC]]. They came out w * 4 x G226 Decoder and Switch
  4 KB (667 words) - 19:53, 30 July 2023
• PDP-11/74
  ...es) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]). [[Category: UNIBUS PDP-11s]]
  2 KB (257 words) - 22:57, 21 August 2021
• RS64 disk drive
  | controller = [[RC11 disk controller|RC11]] ([[UNIBUS]]) head switch =
  2 KB (258 words) - 22:12, 14 August 2023
• RS03/04 disk drive
  | controller = [[RH11 MASSBUS controller|RH11]] ([[UNIBUS]]), [[RH70 MASSBUS controller|RH70]], [[RH10 MASSBUS controller‎|RH10]] head switch =
  3 KB (488 words) - 18:37, 14 August 2023
• Chaosnet interface
  [[Image:CH11-board.png|thumb|right|250px|CH11 Unibus board]] ...name) and '''QBCHNI''' are [[Chaosnet]] [[network interface]]s, for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are identical
  5 KB (709 words) - 18:28, 17 September 2023
• KY11-A Programmer's Console
  ...]s; the 'Bus' light indicates that a [[peripheral]] is in control of the [[UNIBUS]], either for an [[interrupt]], or performing [[Direct Memory Access|DMA]]. The '[[Switch Register]]' is used to enter both addresses and data.
  2 KB (386 words) - 01:41, 6 July 2023
• DM11-BA Modem Control Multiplexor
  ...rial line|synchronous]] and [[asynchronous serial line]]s connected to a [[UNIBUS]] [[device controller]] to be connected to [[modem]]s. It could be set to [ ...kplane]] like the -BB, the -BA plugs into a standard [[UNIBUS]] [[Modified UNIBUS Device|MUD]] slot. It is [[program compatible]] with the DM11-BB (although
  2 KB (268 words) - 02:40, 16 February 2023
• Interlan NI1010A/NI2010A Ethernet Communications Controller
  [[Image:NI1010A.jpg|350px|right|thumb|NI1010A UNIBUS interface]] ...10A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very simil
  6 KB (797 words) - 21:11, 17 August 2022
• DJ11 Asynchronous 16-Line Multiplexer
  The '''DJ11 Asynchronous 16-Line Multiplexer''' is a [[UNIBUS]] [[peripheral]] which provides up to 16 [[asynchronous serial line]]s. Bot could only be set with a pair of [[DIP switch]]es. A group of [[jumper]]s allowed configuration of separate input and out
  5 KB (694 words) - 11:36, 18 February 2023
• DHQ11 asynchronous serial line interface
  ...ronous serial line interface''' is the second [[QBUS]] equivalent to the [[UNIBUS]] [[DH11 asynchronous serial line interface|DH11]] (it is a replacement for It can be set (via a switch) to exactly emulate either a DHV11 or [[DHU11 asynchronous serial line inte
  2 KB (383 words) - 11:47, 17 February 2023
• MM11-B core memory
  ...a 8 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-B was composed of two [[DEC card form factor‎|hex]] b ...11-B did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot b
  3 KB (462 words) - 00:45, 30 July 2023
• MM11-C core memory
  ...a 16 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-C was composed of two [[DEC card form factor‎|hex]] b ...11-C did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot b
  2 KB (414 words) - 00:46, 30 July 2023
• KW11-W Watchdog Timer
  The '''KW11-W Watchdog Timer''' is a [[UNIBUS]] [[peripheral]] which monitors correct operation of a system; unless it is |Switch Relay Register || WDSRR || 772406
  2 KB (266 words) - 23:07, 5 November 2022
• UNIBUS Device Addresses
  '''UNIBUS Device Address''' table; ranges given are inclusive, i.e. a block listed as ...a "17" prepended. A few QBUS [[device controller|devices]] do not exist in UNIBUS form, and are listed in their own right: such cases can be detected by the
  7 KB (927 words) - 11:26, 12 November 2021
• KY11-J Programmer's Console
  ...itch does a variety of things, depending on the position the 'Enable/Halt' switch is in. In the Enable position, the CPU continues operating; in the Halt pos [[Category: UNIBUS PDP-11s]]
  2 KB (372 words) - 18:05, 25 January 2022
• KY11-L to CPU interface
  ...console to request that the CPU [[halt]]; this is done with the standard [[UNIBUS]] [[signal]], SACK, and a pair of additional signals, Halt Request and Gran ...[[grant continuity card]]), the machine will irretrievably 'freeze'; see [[UNIBUS and QBUS termination#SACK turnaround and CPU hangs|SACK turnaround and CPU
  4 KB (650 words) - 16:50, 4 December 2022
• DEC Semiconductor Chips
  | [[UNIBUS]] Request Logic [[#ref_12|[12]]][[#ref_14|[14]]] | CI-2 Switch Chip [[#ref_23|[23]]]
  36 KB (3,420 words) - 05:36, 5 November 2022
• M7850 parity controller
  ...roller''' is an optional accessory for mid-period [[main memory]] on the [[UNIBUS]]; it provides byte [[parity]] for memory units (such as the [[MM11-D core ...wiring for parity and non-parity memory, no hardware changes are needed to switch from non-parity to parity memory with the M7850. When the M7850 is inserted
  3 KB (434 words) - 00:07, 20 April 2024
• UA11 Unibus Analyzer
  [[Image:UA11UnibusAnalyzer.jpg|250px|thumb|right|UA11 Unibus Analyzer]] ...ted by a member of the vintage computer community to help with debugging [[UNIBUS]] problems.
  1 KB (174 words) - 15:31, 9 April 2022
• VAX-11/750 & VAX-11/751 Revision Control
  6.4 DW750 - Second Unibus The implementation of the SID switch reverses the bit positions of
  101 KB (10,182 words) - 14:04, 2 July 2022

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