Difference between revisions of "UNICHANNEL 15 System"
From Computer History Wiki
m (clarify) |
m (→External links: + maint manual, Eng Drwngs) |
||
| Line 6: | Line 6: | ||
{{semi-stub}} | {{semi-stub}} | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [http://bitsavers.org/pdf/dec/pdp15/XVM/DEC-15-HUCMA-B-D_UC15_Nov73.pdf UC15 unichannel-15 system maintenance manual] (DEC-15-HUCMA-B-D) | ||
| + | * [http://bitsavers.org/pdf/dec/pdp15/XVM/UC15_schematics_Aug76.pdf UC15-0 Engineering Drawings] | ||
[[Category: DEC Processors]] | [[Category: DEC Processors]] | ||
Revision as of 22:56, 26 November 2022
The UNICHANNEL 15 System (UC15) is an group of hardware sub-systems which allows a PDP-15 to communicate with a PDP-11 (usually a PDP-11/05) which acts as an I/O front end, partially to offload the PDP-15's CPU, but also to allow PDP-15 systems access to devices which did not have native PDP-15 support, such as the RK05 disk drive. The UC15 includes two separate sub-systems:
- An MX15-B Memory Multiplexer, which allows the PDP-11 (both the CPU, and DMA devices on the PDP-11's UNIBUS) access to the PDP-15's main memory.
- A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of DR11-C general device interface parallel ports on the PDP-11, and a DR15 Device Interface on the PDP-15 end.
External links
- UC15 unichannel-15 system maintenance manual (DEC-15-HUCMA-B-D)
- UC15-0 Engineering Drawings
