FLIP CHIP details
Here are detailed descriptions of FLIP CHIPs:
This is a 8-bit comparator; it compares the value of two 8-bit numbers and provides four outputs which provide the relationships between those two numbers (A=B, A>B, A>=B, and B>=A). An EQUAL IN input, on pin U2, is provided for cascading them.
Inputs (bits numbered in PDP-11 style, with LSB = bit 0):
|P1||EQUAL OUT (L)|
|R1||EQUAL OUT (H)|
This contains eight R/S flip flops. They are formed from a pair of NAND gates interconnected in the usual fashion; they provide inverted S and R inputs, and normal and inverted outputs.
In addition to 16-bit wide input and output, and byte write controls, it also provides an 4 sets of the 4 address inputs, and 4 inputs to select the desired set of address input. (I.e. the address lines are binary encoded, but the address select lines are not.) An internal 4-way mux selects the desired set of address inputs.
There may be a certain amount of variance between which pin is used for which bit; since the card is purely memory, the bits can be re-ordered without harm.
|Address set select||Pin||Address set A||Pin||Address set B||Pin||Address set C||Pin||Address set D||Pin|
Pin BK1 is 'WRITE 15/8', and pin AM2 is 'WRITE 7/0'.
In addition, pin AN1 is a control input of some sort, but it is not yet clear what it does. It is possible that it is some sort of 'output enable'.
This contains six R/S flip flops. They are formed from a pair of NAND gates interconnected in the usual fashion; they provide inverted S and R inputs, and normal and inverted outputs. They differ from the standard SR flops (in the M203, above) in that they have two set inputs.
This is a dual pulse amplifier. It produces a negative-going pulse (nominally 50 nsec wide), triggered by an input transitioning from high to low; the input is a triple-input OR with inverting inputs.