KA820 CPU
The KA820 CPU is a mid-range VAX CPU used in VAX 82xx/83xx series systems. It, and they, use the VAXBI bus to connect their main sub-systems, including the main memory. The CPU also supports the PCI bus (apparently un-related to the bus of the same name on IBM-compatible PCs), used to connect local, low-speed devices.
It used the V-11 chip set (code named 'Scorpio'), fabricated in-house using MOS technology. It made extensive use of pipelining internally; operation throughout the CPU is extensively protected by parity.
Physically, the KA820 is a single board containing a number of custom VLSI chips: one for instruction decoding and execution; one for memory management and cache management; one for floating point; and the VAXBI interconnect interface chip (BIIC). A separate cache is also provided for main memory; another cache, the backup translation buffer (BTB), holds page table entries (this supplements a 'mini-translation buffer' (MTB) held directly on the memory management chip).
The KA820 is a microcoded CPU, using 40-bit micro-instructions. The microcode is mostly held in ROM, but a novel scheme involving a CAM allows it to be 'patched', using a small amount of RAM. An EEPROM holds microcode patches, along with configuration settings, across power-down/up cycles. Front panel functionality is also provided by microcode, along with an on-board asynchronous serial line interface.
External links
- 8200 - documentation at Bitsavers
- KA820/KA825 Processor Technical Manual (EK-KA820-TM-003)
- DEC V-11
- V-11 (1986)
