KDA50 disk controller

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The KDA50 disk controller is an intelligent device controller which connects up to four SDI disks to a QBUS. It uses a radial bus configuration instead of the conventional daisy-chain (serial) method; thus, there is a separate I/O cable going to each disk drive. Direct connection of the KDA50 to each drive maximizes subsystem availability.

It consists of two quad cards, which a mounted in a QBUS backplane of a PDP-11 or VAX, and associated mounting hardware and cables. Dual microprocessors on one of the cards execute independent microprograms to maximize subsystem throughput. Extensive buffering on the other card matches host computer bus capacities to the requirements of high density disk drives. Onboard diagnostic capability with fault reporting both to the host and through LEDs on the modules minimizes repair time.


The two cards are referred to as the processor and SDI modules, according to their principal functions. They communicate with each other by means of two over the back flat cables. Mounting hardware for the cables to the drives consists of locating brackets and bulkhead connectors for the shielded SDI cables leading from the drives to the KDA50's cabinet. An unshielded intra-cabinet SDI cable to run from the connectors to the KDA50 is provided with it.

Processor Module

The KDA50 processor module (M7164) contains two microprocessors, the pair being made up from two 12-bit microsequencers which share a 16-bit ALU. The two microprocessors execute interleaved independent microprograms from ROM, also located on the module. One of the microprocessors, the QBUS microprocessor, handles transactions with the host computer and sets overall policy for KDA50 operation. The other, the drive microprocessor, handles interaction with the disk drives, including error recovery.

The processor module performs all KDA50 interaction with the QBUS. It contains the two registers by which the KDA50 communicates with its host, and a DIP switch pack and a jumper (W1) for setting their addresses. Host software defines the interrupt vector address during KDA50 initialization.

The processor module holds the standard QBUS data transfer chips, which perform cycle level transactions on the QBUS. To avoid interference with QBUS devices having limited buffering, the module contains a bus burst size parameter (called "burst rate" in the documentation) set by software, which sets the number of double-words transferred each time the KDA50 gains control of the QBUS; it can be set from 1 to 8, and defaults to 4.

Four LED indicators on the processor module, together with four similar LEDs on the SDI module, report microdiagnostic detected failures, and indicate which part to replace.

Finally, two other bus grant jumpers (W2 and W3) allow the KDA50 to be plugged into either a Q/Q QBUS backplane or a Q/CD QBUS backplane.

SDI Module

The KDA50 SDI module (M7165) is the physical connection to the disk drives. It conducts data and control transactions through two ribbon cable busses running between it and the microprocessor module.

The SDI module contains terminators for the SDI cables which connect the KDA50 to its drives. Since the SDI is a serial bus, parallel data in KDA50 buffer memory must be converted before being sent to a drive. This is done by two custom LSI serialization/deserialization (SERDES) chips residing on the SDI module. On a write, the SERDES chips serialize data for transfer to the drive. On a read, they perform the opposite function. The SDI module includes switching logic for multiplexing the SERDES among the four drives that may be attached to the KDA50.

Also located on the SDI module is the buffer memory. Consisting of 32 KBytes of static RAM with a word cycle time of 55 nanoseconds, the buffer memory is sufficient for 52 sector buffers (26 KBytes) plus a buffer for 20 host commands (plus one for immediate execution) and the data structures to manage both dynamically.

A major data integrity feature of SDI drives is the 170 bit Reed-Solomon ECC. This ECC has a correction capability of up to 8 10-bit error bursts in a single sector compared to the single 11-bit burst capability of conventional codes. Data passes through a custom LSI chip on its way to the drive, and the ECC is computed in real time. At the end of each sector, the chip supplies the 170 bit ECC to be written with the data. On a read operation, the ECC is both read and recomputed, and the chip supplies the miscompare pattern (if any). If error correction is required, drive microprocessor microcode performs it.


The KDA50 has only two registers:

Register Abbreviation Address
Initialization and Polling Register KDAIP 172150
Status/Address Register KDASA 172152

The addresses given assume the standard base address (0172150); if this is changed, so will the addresses.

See also

Further reading

  • KDA50 Service Manual (not online)
  • KDA50 Field Maintenance Print Set MP-01423 (not online)

External links