Difference between revisions of "PDP-10 memories"
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Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set. | Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set. | ||
| + | |||
| + | As was common with machines of that era, compatible PDP-10 main memory units were produced and sold by manufacturers other than [[Digital Equipment Corporation|DEC]]; some (but by no means all) are listed below. | ||
==Memory systems== | ==Memory systems== | ||
| − | 18-bit external: | + | 18-bit external (DEC): |
* [[MA10 core memory|MA10]] | * [[MA10 core memory|MA10]] | ||
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* [[MD10 core memory|MD10]] | * [[MD10 core memory|MD10]] | ||
| − | 22-bit external: | + | 18-bit external (others): |
| + | |||
| + | * [[Fabritek Core Memory]] | ||
| + | |||
| + | 22-bit external (DEC): | ||
* [[ME10 core memory|ME10]] | * [[ME10 core memory|ME10]] | ||
| Line 24: | Line 30: | ||
* [[MH10 core memory|MH10]] | * [[MH10 core memory|MH10]] | ||
| − | Internal: | + | 22-bit external (others): |
| + | |||
| + | * [[Ampex ARM10|Ampex ARM-10L]] | ||
| + | |||
| + | Internal (DEC): | ||
* [[MA20 core memory|MA20]] | * [[MA20 core memory|MA20]] | ||
| Line 31: | Line 41: | ||
* [[MG20 MOS memory|MG20]] | * [[MG20 MOS memory|MG20]] | ||
| − | The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R) | + | Internal (others): |
| + | |||
| + | * [[Ampex ARM20]] | ||
| + | |||
| + | The first two groups are all multi-port (necessary to allow [[mass storage]] on [[channel]]s to do [[Direct Memory Access|DMA]]; generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R); all the DEC ones except the MF20 and MG20 were core. | ||
[[Category: PDP-10 Memories]] | [[Category: PDP-10 Memories]] | ||
Revision as of 11:59, 22 April 2022
PDP-10 memories were generally all multi-port memory units. The PDP-10 CPU used one port (one per CPU in multi-processor systems); the others are used by channels for mass storage, such as disks. Interleaving was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were core, and supported parity for error detection; the others were MOS DRAM, and used ECC to protect the memory contents.
There were three generations of main memory bus (which ran sequentially through memory units to a terminator), and memory units to them. The first two were the so-called 'external memory bus', in KA (18-bit address) and KI (22-bit) forms (for the KA10, and KI10 and early KL10, respectively), although they also had protocol differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the logic family it interfaced to.) The differences between the two external bus types required a KI10-M Memory Bus Adapter if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a DMA20 Memory Bus Adapter.
The S-Bus (and the later version, the X-Bus, used with MOS 'internal' memory) performs memory transfers in blocks of up to four words, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.
Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set.
As was common with machines of that era, compatible PDP-10 main memory units were produced and sold by manufacturers other than DEC; some (but by no means all) are listed below.
Memory systems
18-bit external (DEC):
18-bit external (others):
22-bit external (DEC):
22-bit external (others):
Internal (DEC):
Internal (others):
The first two groups are all multi-port (necessary to allow mass storage on channels to do DMA; generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R); all the DEC ones except the MF20 and MG20 were core.
