KA10

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KA10
Ka10.jpg
KA10-based PDP-10 system
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Design Started: January, 1966
Year First Shipped: September, 1967
Form Factor: mainframe
Word Size: 36 bits
Logic Type: silicon transistors and diodes
Design Type: asynchronous with hardware subroutines
Clock Speed: 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous)
Memory Speed: 1.0 μsec (fast), 1.8 μsec (slow)
Physical Address Size: 18 bits (normal), 19/20 (ITS paging box), ?? (TENEX paging box)
Virtual Address Size: 18 bits
Memory Management: dual base and bounds register pairs (non-customized machines)
Operating System: Monitor, ITS, WAITS, TENEX
Predecessor(s): PDP-6
Successor(s): KI10
Price: US$150K (CPU), US$300-700K (system)


The front panel of a KA10

The KA10 was the first generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of discrete transistors, on short single FLIP CHIP cards, plugged into large custom-wired backplanes.

It had hardware support for time-sharing (two modes, 'User' and 'Executive'), as well as base and bounds memory management hardware. These were used in the first DECsystem-10 models, running TOPS-10.

B-series FLIP CHIP used in the KA10 CPU

It was also the machine on which the ITS and TENEX operating systems were developed, after the machines were modified to provide paging.

See also

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