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• KA11 CPU
  ...s connection is to allow the KA11 to serve as the 'bus arbitrator' for the UNIBUS. Only the Data Paths section can pass data to the Bus Interface section. The DATIP (read with expected write to follow) UNIBUS cycle, especially useful for [[core memory]] (which must write the date bac
  9 KB (1,356 words) - 23:10, 29 February 2024
• KDF11 CPUs
  * [[KDF11-U CPU]] - M7133 - [[UNIBUS]] hex-width CPU used in the [[PDP-11/24]] ...he KEF11-A is installed; is unusual that it can plug into either a QBUS or UNIBUS [[backplane]], since it draws only power from the backplane - all [[signal]
  3 KB (394 words) - 13:49, 29 March 2022
• KDF11-U CPU
  ...e 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It plugs into a custom ...DF11-U usually operates with the optional [[UNIBUS map]] board, the [[KT24 UNIBUS map option|KT24]].
  6 KB (1,087 words) - 16:16, 6 February 2024
• KE11-F Floating Instruction Set
  [[Category: PDP-11 UNIBUS Processors]]
  2 KB (246 words) - 02:34, 12 October 2022
• KD11-E CPU
  ...nd the '''M7266''' Control module. They plugged into a modified [[Modified UNIBUS Device|MUD]] [[backplane]], the [[DD11-P backplane]], which was customized ...ctionality of the KY11-B [[KY11-L to CPU interface|is performed]] over the UNIBUS, and a pair of backplane lines.
  5 KB (791 words) - 02:23, 6 December 2022
• KD11-EA CPU
  [[Category: PDP-11 UNIBUS Processors]]
  6 KB (1,045 words) - 22:47, 31 March 2022
• KY11-LA Operator's Console
  In addition to several standard [[UNIBUS]] signals (SACK, INIT, DCLO and ACLO), it also used a pair of additional ba [[Category: PDP-11 UNIBUS Processors]]
  2 KB (358 words) - 18:29, 3 April 2022
• Category:PDP-11 Processors
  While all [[PDP-11]] processors used either the [[UNIBUS]] or [[QBUS]], these busses were used by other [[Central Processing Unit|CP [[Category: DEC Processors]]
  15 members (2 subcategories, 0 files) - 16:26, 16 December 2018
• Template:InfoboxVAX-Data
  Num-proc = Number of processors BUS-UNIBUS = UNIBUS details
  12 KB (1,039 words) - 13:24, 10 March 2024
• VAX 8200
  ...t|VAXBI]] [[bus]]; it uses the [[KA820 CPU]]. It can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
  2 KB (317 words) - 04:02, 19 May 2024
• VAX 8300
  ...ect|VAXBI]] [[bus]], using the [[KA820 CPU]]; it can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
  2 KB (287 words) - 14:43, 19 May 2024
• KS10
  The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture ...Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the syste
  8 KB (1,237 words) - 19:48, 14 July 2023
• FP11-A Floating-Point Processor
  [[Category: PDP-11 UNIBUS Processors]]
  4 KB (734 words) - 02:17, 13 October 2022
• KK11-A Cache Memory
  ...ing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 [[parity]] bits (one for the tag); and two valid b [[Category: PDP-11 UNIBUS Processors]]
  4 KB (553 words) - 02:36, 12 October 2022
• KD11-A CPU
  ...US [[Small Peripheral Controller|SPC]] slot; that slot also contained the 'UNIBUS out'. | 9 || colspan="2" style="text-align:center;" | UNIBUS Out || colspan="4" style="text-align:center;" | SPC
  4 KB (588 words) - 05:52, 8 April 2024
• DL10 PDP-11 Data Link
  ...also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connect ...DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
  5 KB (664 words) - 17:27, 7 November 2023
• MINITS
  ...[graphics terminal]]s, and provide [[Chaosnet]] [[front end]]s to [[KL10]] processors. * [[UNIBUS Experimental Ethernet interface|3 Mbit Ethernet]] interface
  3 KB (347 words) - 08:50, 27 February 2024
• KD11-B CPU
  ...as a bus arbitrator, so that the machine can be a 'slave' processor, on a UNIBUS controlled by another CPU. [[Category: PDP-11 UNIBUS Processors]]
  11 KB (1,726 words) - 21:07, 2 July 2023
• KB11-A CPU
  In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
  3 KB (395 words) - 21:08, 2 July 2023
• KB11-D CPU
  In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
  2 KB (307 words) - 12:32, 11 October 2022

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