KD11-EA CPU

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The KD11-EA CPU was the second CPU version for the PDP-11/34; it consisted of two hex boards, the M8265 Data Paths module and the M8266 Control module.

It also supported the optional FP11-A floating point unit and/or the KK11-A cache (it could work with either, or both).

Apparently, the microcode address space was increased by one bit in the KD11-EA over the KD11-E, probably to support the extra micro-code needed for the floating point instructions.

KY11-LB Interface

Like the KD11-E, it also supported the KY11-LB Programmer's Console, including the maintainence functionality which allowed the CPU's microcode to be single-stepped.

The interface to the KY11-LB was carried over two 10-wire cables connected to Berg headers (denominated J1 and J2) on the M8266 module. The pinout for P1 is the same as for the KD11-E; P2 has additional signals (other than uPC08) added in the KD11-EA, though:

J2:

  1. Micro-PC 08
  2. FP11-A Attached
  3. Unused
  4. Unused
  5. Unused
  6. Micro-PC 09
  7. Service Br Power Fail
  8. Load Instruction Register
  9. Power Fail Br Pending
  10. Unused