KY11-LB Programmer's Console
The KY11-LB Programmer's Console was an option for the PDP-11/04 and the PDP-11/34 (the units for the two machines differed only in the number painted on the plastic insert). It provided the functionality of a conventional 'lights and switches' front panel.
To perform the basic functions of the console, it communicated with the PDP-11 CPU and main memory over the UNIBUS; a pair of additional backplane lines (Halt Request and Grant) communicate with the CPU, to request that the main CPU halt, and for the CPU to acknowledge that it has honoured that request.
To enable the extended maintenance functions which the KY11-B can perform, one (-11/04) or two (-11/34) optional flat cables connect the KY11-B card to a PDP-11 CPU card.
The front panel had an octal keypad, a 6-digit LED display which showed address and data information, several individual indicator LEDs, and the following function keys:
- CLR - Clear
- LAD - Load Address
- DIS AD - Display Address
- LSR - Load Switch Register
- EXAM -Examine
- DEP - Deposit
- CNTRL - Control - Used to enable the following keys:
- INIT - Initialize
- HALT/SS - Halt/Single-Step (the latter without 'Control')
- CONT - Continue
In addition, several other maintenance functions were actuated by use of the 'Control' key along with various numeric keys; in particular, the microcode of the PDP-11 processor can be single-stepped in maintenance mode.
The front panel also had six indicators:
- SR DISP - Switch Register Display
- BUS ERR - Bus Error
- MAINT - Maintenance
- BATT - Battery
- DC ON
The interface to the CPU, for maintenance purposes, carried the micro-PC (from the CPU), and 'Manual Clock Enable' and 'Manual Clock' lines.
The pinout for J2 (used in both) is (pin identifications are given in both numeric and alphabetic forms, as some engineering drawings use one, and some the other):
- A - Micro-PC 04
- C - Micro-PC 01
- E - Micro-PC 02
- H - Micro-PC 03
- K - Manual Clock Enable
- B - Micro-PC 00
- D - Micro-PC 05
- F - Micro-PC 06
- J - Micro-PC 07
- L - Manual Clock
The pinout for J3 (only used with the -11/34) is:
- A - Micro-PC 08
- FP11-A Attached
- B - Micro-PC 09
- Service Br Power Fail
- Load Instruction Register
- Power Fail Br Pending
Internal Details and Versions
The ROM is contained in four 512x4-bit PROMs:
- 23-347-A9 Code PROM low bits bank 1
- 23-348-A9 Code PROM high bits bank 1
- 23-345-A9 Code PROM low bits bank 2
- 23-346-A9 Code PROM high bits bank 2
There is one other smaller PROM (DEC part number 23-123-A1) which converts from uCPU cycle type (ROM read, RAM read/write, I/O cycles) to the control lines needed to implement all those functions.
There are actually two versions of the card. In the later one, i) the four 8093 quad tri-state buffers between the UNIBUS data lines, and the internal bus, are replaced by 74173's, and ii) incoming SSYN is synchronized with the i8008's clock. Although the PCB is slightly different, the ROMs are all the same.
Cable Connection and Documentation Error
The KY11-LB maintenance manual contains a major error, in describing the configuration of the flat cable that connects the front panel and the UNIBUS interface module. This is covered in Chapter 9, "Installation", which includes two figures, Figures 9-4 and 9-5.
Those figures show the 20-conductor flat cable with the red edge stripe oriented toward the outer edge of the front panel PCB (correct), and also toward the outer edge of the M7859 (WRONG). On the M7859, the red stripe edge needs to be away from the outer edge of the board.
If it is plugged in as shown in these figures, the machine will not operate: the four 'RUN/SR DISP/BUS ERR/MAINT' lights will be on, but nothing else, and it will not respond to any keys. Fortunately, plugging the cable in reversed does not damage anything; simply reverse the cable, and all will be well.
- EK-KY1LB-MM-001, KY11-LB programmer's console/interface module operation and maintenance manual