Modified UNIBUS Device
It differed from the older SPC slot in that it was a hex-height slot, and used the pins (in the A-B connectors) to carry UNIBUS signals - mostly pin-compatible with the original dual UNIBUS slot, but there were a few important differences.
The most important was that since the standard UNIBUS dual connector only contains one pin per bus grant line (suitable only for an 'in' or 'out' UNIBUS connector), not separate 'grant in' and 'grant out' pins (as on the QBUS), a full-function UNIBUS slot is not possible with only two connectors. The MUD connectors therefore do not contain grants; those pins were recycled for other functions.
Some re-assigned pins contain a number of lines for communication between a parity controller, and parity-capable main memory boards plugged into that backplane; others carry additional voltages (primarily for core memory).
Technically, a MUD slot only describes the A-B connectors; most backplanes also provided SPC functionality in the C-F connectors (needed for signals for interrupts or DMA, for devices which did those), with most UNIBUS signals present in both; the combination is sometimes called a 'MUD/SPC' slot.
The DD11-C (4-slot) and DD11-D (9-slot) and later backplanes generally provided MUD slots, not the earlier SPC slots; however, generally the slots in these later backplanes are MUD/SPC - other than the entrance and exit slots, which have normal two-slot UNIBUS in/out in A-B, and SPC in C-F.
MUD/SPC slots were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx), not the 'pseudo-UNIBUS' rows A/B.
A board plugged into a MUD/SPC slot generally had a header which routed the grant (and matching request) line for the desired priority level to the on-board interrupt circuity, and passed the other grant lines through.
The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot.
Un-occupied slots needed to have a grant continuity card installed.
The added lines for communication between a parity controller and parity-capable memory boards were Parity Detect (used to let memory boards know that a parity controller is present); Internal SSYN (used by memory boards to let the parity controller know that their data is ready); and Parity P0 and Parity P1 (parity data).
The additional voltages were + and -15V, -5V, and +20V. Note that in some machines (the PDP-11/44 and PDP-11/24) the +15V/-15 pins actually contain +12V/-12V, for use by the MS11-M MOS memory card, which needs those voltages. +15V/-15V are available in the SPC portion of some such slots.
The pins which were added (changed) to create MUD are:
- AB2 - Test Point
- AN1 - Parity P1
- AP1 - Parity P0
- AR1 - -15/12 Battery
- AS1 - -15/12 Battery
- AU1 - +20V (core)
- AV1 - +20V (core)
- AV2 - +20V (core)
- BA1 - Reserved
- BB1 - Reserved
- BB2 - Test Point
- BD1 - +5V Battery
- BE1 - Internal SSYN
- BE2 - Parity Detect
- BV2 - -5V (core)
Since grants could not be supported in the number of pins available in a dual connector, all grant pins were removed, along with some ground pins.
The pins which changed function from normal UNIBUS to MUD are listed below.
- AB2 - Ground
- AN1 - Ground
- AP1 - Ground
- AR1 - Ground
- AS1 - Ground
- AU1 - NPG
- AV1 - BG7
- AV2 - Ground
- BA1 - BG6
- BB1 - BG5
- BB2 - Ground
- BD1 - Ground
- BE1 - Ground
- BE2 - BG4
- BV2 - Ground
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Clones: CM 1420