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Pdp11 44.jpg
PDP-11/44 from a sales brochure.
Manufacturer: Digital Equipment Corporation
Architecture: PDP-11

The PDP-11/44 was a high performance UNIBUS PDP-11 system; in some senses a lower-cost successor to the PDP-11/70, although without the very high main memory bandwidth and I/O bandwidth to mass storage of the -11/70, as it lacked the latter's Main Memory Bus and integrated MASSBUS, relying instead on the UNIBUS, and EUB. Its CPU, the KD11-Z, was the last PDP-11 CPU to be made out of discrete chips, and not a microprocessor.

The -11/44 used the EUB for its bus to main memory, allowing it to have up to 4 mega-bytes of main memory. All devices were attached to a semi-separate UNIBUS (it and the EUB shared data lines, but not address lines); DMA devices could gain access to the memory via a UNIBUS map which connected the two, and mapped UNIBUS addresses to main memory addresses.

A PDP-11/44 setup

Full PDP-11 Memory Management and a cache (the KK11-B) were standard on all -11/44's. It also supported the optional FP11-F floating point (full FP11 floating point), and/or the KE44-A Commercial Instruction Set Processor (the PDP-11 Commercial Instruction Set).

The -11/44 initially shipped with MS11-M; the MS11-P became available later, and was also useable in the -11/44.

Its main mounting box was the new BA11-A mounting box.


Quoting http://www.xs4all.nl/~geerol/en/GAL/index.html (1979) The PDP 11/44 (hostname "gigant") is a low-cost successor of the PDP 11/70. The 11/70, brought to the market in 1975, was the first "large" PDP. Large means a 22 bit address space and a memory limit of 4MB. Do keep in mind that user programs are still limited to 16 bit addressing and hence restricted to a limit of just 2x 64KB, when using separated I&D.

The cost of a new 11/44 has been about half of the listprice of an 11/70. The PDP 11/44 had no Massbus like the /70 has, so it was not possible to use diskdrives with a transfer rate too high.


Quoting: 1979. A middle-class -11. It had the 22-bit UNIBUS map and MMU as standard (up to 2 Mwords on a separate CPU-memory interconnect, called the PAX Memory Bus). The CPU consists of 5 boards, plus one for the FPP (FP11-F, optional), and two CIS (KE44-A, optional). Features: 8 KByte cache, ODT, 2 SLU's (Serial Line Units: console + TU58 console media), RTC (Real-Time Clock), kernel/supervisor/user modes.

The machine also had an almost-FEP (front-end processor) console, based on the Intel i8088, running from PROM. There was no QBUS equivalent.

Trivia: This was the last non-microprocessor-based PDP-11.

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