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PDP-8/S front panel inlay
Manufacturer: DEC
Architecture: PDP-8
Year Introduced: 1967
Year Discontinued: 1970
Form Factor: minicomputer
Word Size: 12 bits
Logic Type: DTL
Design Type: clocked random logic
Clock Speed: 1.333Mhz (per bit)
Cycle Time: 10.5 μseconds (per word)
Memory Speed: 8 μseconds
Physical Address Size: 32k words (requires optional MC8S)
Virtual Address Size: 4k words
Memory Management: bank select
Bus Architecture: Negative I/O Bus
Predecessor(s): PDP-8
Successor(s): PDP-8/L

The PDP-8/S was DEC's attempt to produce a 'cheaper' PDP-8. It was a serial implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.

The PDP-8 was constructed with discrete transistors, packaged into DEC's FLIP CHIP technology. It could perform an addition to the accumulator in 64 μseconds. It had parity on the main memory as standard, not optional.


Options included:

  • DB8S Data Break, needed for data break on the I/O bus
  • MC8S Memory Extension Control, which was needed to support more than 4k words of memory
  • MM8S Memory Module
  • ME8S Memory Extension, holds two MM8S


PDP-8/S in the Tekniska Museet in Stockholm, Sweden