PDP-8/S front panel inlay
|Word Size:||12 bits|
|Design Type:||clocked random logic|
|Memory Speed:||8 μseconds|
|Physical Address Size:||32KW (requires optional MC8S)|
|Virtual Address Size:||4KW|
|Memory Management:||bank select|
|Bus Architecture:||Negative I/O Bus|
The PDP-8/S was DEC's attempt to produce a 'cheaper' PDP-8. It was a serial implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
The PDP-8 was constructed with discrete transistors, packaged into DEC's FLIP CHIP technology. It could perform an addition to the accumulator in 64 μseconds. It had parity on the main memory as standard, not optional.
- DB8S Data Break, needed for data break on the I/O bus
- MC8S Memory Extension Control, which was needed to support more than 4K words of memory
- MM8S Memory Module
- ME8S Memory Extension, holds two MM8S
|v • d • e PDP-8 Computers, Software and Peripherals|
|PDP-8s: PDP-5 • PDP-8 • LINC-8 • PDP-8/S • PDP-8/I • PDP-8/L • PDP-12 • PDP-8/E • PDP-8/F • PDP-8/M • PDP-8/A|