Difference between revisions of "KL10"
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| design type = clocked synchronous, [[microprogrammed]] | | design type = clocked synchronous, [[microprogrammed]] | ||
| clock speed = 500 nsec | | clock speed = 500 nsec | ||
| − | | memory speed = 1.0 μsec (initial [[core memory]]), | + | | memory speed = 1.0 μsec (initial [[core memory]]), 500 nsec (later [[MOS]] [[main memory]]) |
| memory mgmt = [[paging]], 512-word pages | | memory mgmt = [[paging]], 512-word pages | ||
| operating system = [[TOPS-10]], [[TOPS-20]], [[TENEX]] | | operating system = [[TOPS-10]], [[TOPS-20]], [[TENEX]] | ||
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Like its predecessor, the KI10, it was initially released in a single-[[processor]] version; a two-CPU version was released later. | Like its predecessor, the KI10, it was initially released in a single-[[processor]] version; a two-CPU version was released later. | ||
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| + | ===External Links== | ||
| + | |||
| + | * [https://dodlithr.blogspot.com/2014/04/digitals-decsystem-20-part-5-cpu-kl10.html Digital's DECSYSTEM-20 - Part 5 - CPU (KL10)] | ||
Revision as of 00:02, 6 August 2017
| KL10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | January, 1972 |
| Year First Shipped: | June, 1975 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | ECL ICs |
| Design Type: | clocked synchronous, microprogrammed |
| Clock Speed: | 500 nsec |
| Memory Speed: | 1.0 μsec (initial core memory), 500 nsec (later MOS main memory) |
| Physical Address Size: | 22 bits |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, TENEX |
| Predecessor(s): | KI10 |
| Successor(s): | none |
| Price: | US$250K (CPU), US$600K-1.2M (system) |
The KL10 was the third generation of PDP-10 processors. It was built out of ECL, on hex cards.
It was used in the DECsystem-10 models 1080 and 1090 systems (with an external memory bus, compatible with the earlier KA10 and KI10), and the DECSYSTEM-20 20xx systems (with an internal memory bus).
Like its predecessor, the KI10, it was initially released in a single-processor version; a two-CPU version was released later.
