KK11-B Cache Memory

The KK11-B Cache Memory was a standard part of the KD11-Z CPU of the PDP-11/44, a high-speed cache for the CPU.

Physically, it was a single hex board, the M7097.

Technical detail

The KK11-B contained 4096 cache entries of high-speed DRAM, in the form of 30 4096x1 static RAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of main memory could be found), with write-through, and a block size of one word.

Each cache entry was 30 bits wide, containing two data bytes; a tag field for cache entries, 9 bits wide (covering Extended UNIBUS address bits 21-13); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).

Only memory o the Extended UNIBUS was cached, not any memory which might be present on the ordinary UNIBUS (normally used only for I/O).

Registers

The cache registers are mostly at the same locations as some of the memory/cache registers in the PDP-11/70, but they are generally incompatible with those in the /70.

Register	Abbreviation	Address
Cache Error Register	CME	777744
Cache Control/Status Register	CCSR	777746
Cache Maintenance Register	CMR	777750
Cache Hit Register	CHR	777752
Cache Memory Data Register	CDR	777754

See also

• KK11-A Cache Memory

External links

• PDP-11/44 System Technical Manual - the KK11-B is covered in Section 6-12 (pp. 242-258 of the PDF)
• 11X44 Field Maintenance Print Set - the KK11-B Field Maintenance Print Set (MP00811) is on pp. 106-128 of the PDF