KK11-B Cache Memory
Physically, it was a single hex board, the M7097.
The KK11-B contained 4096 cache entries of high-speed DRAM, in the form of 30 4096x1 static RAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of main memory could be found), with write-through, and a block size of one word.
Each cache entry was 30 bits wide, containing two data bytes; a tag field for cache entries, 9 bits wide (covering Extended UNIBUS address bits 21-13); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).
The cache registers are mostly at the same locations as some of the memory/cache registers in the PDP-11/70, but they are generally incompatible with those in the /70.
|Cache Error Register||CME||777744|
|Cache Control/Status Register||CCSR||777746|
|Cache Maintenance Register||CMR||777750|
|Cache Hit Register||CHR||777752|
|Cache Memory Data Register||CDR||777754|