Difference between revisions of "KI10"
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| virtual address = 18 bits | | virtual address = 18 bits | ||
| logic type = [[transistor-transistor logic|TTL]] [[IC]]s | | logic type = [[transistor-transistor logic|TTL]] [[IC]]s | ||
| − | | design type = | + | | design type = clocked synchronous |
| − | | | + | | instruction speed = 1 μsec |
| memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | ||
| memory mgmt = [[paging]], 512-word pages | | memory mgmt = [[paging]], 512-word pages | ||
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[[Image:Sys37a.jpg|thumb|300px|left|KI10 at Tymshare]] | [[Image:Sys37a.jpg|thumb|300px|left|KI10 at Tymshare]] | ||
| − | The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on [[FLIP CHIP]] cards. | + | The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on small [[FLIP CHIP]] cards. |
It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later. | It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later. | ||
It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware. | It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware. | ||
| + | |||
| + | A few documents refer to the KI10-based system as PDP-10I. | ||
==Busses== | ==Busses== | ||
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[[Image:KBusQCUnlatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in unlatched position)]] | [[Image:KBusQCUnlatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in unlatched position)]] | ||
| − | Although the KI10 [[CPU]] provided two each | + | Although the KI10 [[Central Processing Unit|CPU]] provided two each of [[PDP-10 Memory Bus]] and [[PDP-10 I/O Bus]] connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet). |
| + | |||
| + | The KI10 Memory Bus is slightly different from that of the [[KA10]]; KA10-style memories can be used on a KI10, but require use of a [[KI10-M Memory Bus Adapter]] (see Section 6.7 of the KI10 Central Processor Maintenance Manual). | ||
==External links== | ==External links== | ||
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** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/A_Document_On_The_KI10_Apr73.pdf A Document On The KI10] | ** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/A_Document_On_The_KI10_Apr73.pdf A Document On The KI10] | ||
** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/KI10ProcMaintMan.pdf KI10 Central Processor Maintenance Manual] | ** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/KI10ProcMaintMan.pdf KI10 Central Processor Maintenance Manual] | ||
| + | * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1] | ||
| + | * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2] | ||
[[Category: PDP-10 Processors]] | [[Category: PDP-10 Processors]] | ||
Latest revision as of 12:23, 5 November 2023
| KI10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | December, 1969 |
| Year First Shipped: | May, 1972 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | TTL ICs |
| Design Type: | clocked synchronous |
| Instruction Speed: | 1 μsec |
| Memory Speed: | 1.0 μsec (fast), 1.8 μsec (slow) |
| Physical Address Size: | 22 bits |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TENEX, TYMCOM-X |
| Predecessor(s): | KA10 |
| Successor(s): | KL10 |
| Price: | US$200K (CPU), US$500K-1M (system) |
The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on small FLIP CHIP cards.
It was the first PDP-10 model to provide paging in its as-shipped form, with 512-word pages. It was initially released in a single-CPU version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.
It was used in later DECsystem-10 models, running TOPS-10. Via a series of kludges, it was also possible to run TENEX on the as-shipped hardware.
A few documents refer to the KI10-based system as PDP-10I.
Busses
Although the KI10 CPU provided two each of PDP-10 Memory Bus and PDP-10 I/O Bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).
The KI10 Memory Bus is slightly different from that of the KA10; KA10-style memories can be used on a KI10, but require use of a KI10-M Memory Bus Adapter (see Section 6.7 of the KI10 Central Processor Maintenance Manual).
