Difference between revisions of "KDJ11-D CPU"
(+KDJ11-D/S CPU System Maintenance man, typos) |
(→ROM Versions) |
||
| (6 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
| − | The '''KDJ11-D''' CPU board, formally named the '''KDJ11-D/S''' in the later variant (below), is the third [[QBUS]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]] of the [[PDP-11]] of the [[KDJ11 CPUs]]. It is a [[DEC card form factor|quad-height]] board, the '''M7554'''; it is available in the so-called [[S-box]] format, for the [[BA200]] enclosure. It was used in the [[PDP-11/53]]. | + | [[Image:KDJ11-D.jpg|200px|thumb|right|KDJ11-D; later variant, 1.5MB version]] |
| + | |||
| + | The '''KDJ11-D''' CPU board, formally named the '''KDJ11-D/S''' in the later variant (below), is the third [[QBUS]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]] of the [[PDP-11]] of the [[KDJ11 CPUs]]. It is a [[DEC card form factor|quad-height]] board, the '''M7554'''; it is available in the so-called [[S-box]] format, for the [[BA200]] enclosure. It was used in the [[PDP-11/53]] and the [[DECserver 500]] Series [[Terminal Server]]. | ||
Its principal difference from the KDJ11-B is that the KDJ11-D does not support the [[Private Memory Interconnect]] [[bus]] (a high-performance variant of the QBUS); instead, it provides either .5MB or 1.5 MB (depending on the exact model) of on-board [[main memory]] (with byte [[parity]]). (Additional memory, up to the 4MB limit of the J-11, can be utilized over the QBUS.) | Its principal difference from the KDJ11-B is that the KDJ11-D does not support the [[Private Memory Interconnect]] [[bus]] (a high-performance variant of the QBUS); instead, it provides either .5MB or 1.5 MB (depending on the exact model) of on-board [[main memory]] (with byte [[parity]]). (Additional memory, up to the 4MB limit of the J-11, can be utilized over the QBUS.) | ||
| Line 5: | Line 7: | ||
It also does not support the [[FPJ11 floating point accelerator]] [[integrated circuit|chip]] (used to speed up the [[FP11 floating point|FP11]] implementation in the J-11), and it does not have a [[cache]]. It also only supports level 4 [[interrupt]]s on the QBUS (although requests at other levels are honoured; just treated as if they were level 4). | It also does not support the [[FPJ11 floating point accelerator]] [[integrated circuit|chip]] (used to speed up the [[FP11 floating point|FP11]] implementation in the J-11), and it does not have a [[cache]]. It also only supports level 4 [[interrupt]]s on the QBUS (although requests at other levels are honoured; just treated as if they were level 4). | ||
| − | Similarly to the KDJ11-B, it also provides a | + | Similarly to the KDJ11-B, it also provides a built-in [[asynchronous serial line|serial]] line for console, and [[Read-only memory|ROM]]s to contain diagnostic and [[bootstrap]] programs. The KDJ11-D provides a second SLU, referred to as SLU 1 or DL1 in the documentation, at base address 17776500Q, vector 300Q. The Module User's Guide suggests that this SLU can be used for a printer, but the base address and vector make SLU 1 usable with default [[TU58]] configurations, whether a real drive or emulated. |
| − | ==Versions== | + | ==Board Versions== |
The KDJ11-D comes in two quite different main variants; unfortunately, they use the same board number, so a visual inspection is needed to know which variant a particular KDJ11-D board is. | The KDJ11-D comes in two quite different main variants; unfortunately, they use the same board number, so a visual inspection is needed to know which variant a particular KDJ11-D board is. | ||
| Line 13: | Line 15: | ||
Versions of the early variant all utilize a large number of discrete [[logic]] chips, and hold 512KB of memory. The later, 're-engineered' (as the documentation calls it) variant, has moved most of the logic into two [[gate array]]s (DC7063 for control, and DC7064 for [[data path]]s), which made room for up to 1.5MB of memory. | Versions of the early variant all utilize a large number of discrete [[logic]] chips, and hold 512KB of memory. The later, 're-engineered' (as the documentation calls it) variant, has moved most of the logic into two [[gate array]]s (DC7063 for control, and DC7064 for [[data path]]s), which made room for up to 1.5MB of memory. | ||
| − | The two versions are fairly distinct, visually: in the early variant, with the card oriented with the contact fingers at the bottom, the large DCJ11 CPU chip is placed horizontally in the centre of the card; in the re-engineered variant, it is placed vertically, on the right-hand edge of the card. (The two large chips next to it are the two gate arrays.) | + | The two versions are fairly distinct, visually: in the early variant, with the card oriented with the contact fingers at the bottom, the large DCJ11 CPU chip is placed horizontally in the centre of the card; in the re-engineered variant (shown above), it is placed vertically, on the right-hand edge of the card. (The two large chips next to it are the two gate arrays.) |
The following versions of the 'early' variant exist: | The following versions of the 'early' variant exist: | ||
| Line 29: | Line 31: | ||
There .5MB/1.5MB versions are easy to tell apart visually: the .5MB cards have only two horizontal rows of [[DRAM]] chips in the large array on the left-hand side; on the 1.5MB cards, all six rows are present. | There .5MB/1.5MB versions are easy to tell apart visually: the .5MB cards have only two horizontal rows of [[DRAM]] chips in the large array on the left-hand side; on the 1.5MB cards, all six rows are present. | ||
| + | |||
| + | ==ROM Versions== | ||
| + | |||
| + | The KDJ11-D supports the following ROMs: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | | DEC Part Number || Version || Socket || Size || Application || Notes | ||
| + | |- | ||
| + | | 23-204E5-00 || 1.0 || E26 (High) || 16KB || [[PDP-11/53]] || Supports only English and Spanish language options | ||
| + | |- | ||
| + | | 23-205E5-00 || 1.0 || E34 (Low) || 16KB || [[PDP-11/53]] || Supports only English and Spanish language options | ||
| + | |- | ||
| + | | 23-261E5-00 || 2.0 || E26 (High) || 16KB || [[PDP-11/53]] || Multi-language support, latest version | ||
| + | |- | ||
| + | | 23-262E5-00 || 2.0 || E34 (Low) || 16KB || [[PDP-11/53]] || Multi-language support, latest version | ||
| + | |} | ||
==External links== | ==External links== | ||
Latest revision as of 15:09, 27 July 2024
The KDJ11-D CPU board, formally named the KDJ11-D/S in the later variant (below), is the third QBUS CPU card using the J-11 chip set of the PDP-11 of the KDJ11 CPUs. It is a quad-height board, the M7554; it is available in the so-called S-box format, for the BA200 enclosure. It was used in the PDP-11/53 and the DECserver 500 Series Terminal Server.
Its principal difference from the KDJ11-B is that the KDJ11-D does not support the Private Memory Interconnect bus (a high-performance variant of the QBUS); instead, it provides either .5MB or 1.5 MB (depending on the exact model) of on-board main memory (with byte parity). (Additional memory, up to the 4MB limit of the J-11, can be utilized over the QBUS.)
It also does not support the FPJ11 floating point accelerator chip (used to speed up the FP11 implementation in the J-11), and it does not have a cache. It also only supports level 4 interrupts on the QBUS (although requests at other levels are honoured; just treated as if they were level 4).
Similarly to the KDJ11-B, it also provides a built-in serial line for console, and ROMs to contain diagnostic and bootstrap programs. The KDJ11-D provides a second SLU, referred to as SLU 1 or DL1 in the documentation, at base address 17776500Q, vector 300Q. The Module User's Guide suggests that this SLU can be used for a printer, but the base address and vector make SLU 1 usable with default TU58 configurations, whether a real drive or emulated.
Board Versions
The KDJ11-D comes in two quite different main variants; unfortunately, they use the same board number, so a visual inspection is needed to know which variant a particular KDJ11-D board is.
Versions of the early variant all utilize a large number of discrete logic chips, and hold 512KB of memory. The later, 're-engineered' (as the documentation calls it) variant, has moved most of the logic into two gate arrays (DC7063 for control, and DC7064 for data paths), which made room for up to 1.5MB of memory.
The two versions are fairly distinct, visually: in the early variant, with the card oriented with the contact fingers at the bottom, the large DCJ11 CPU chip is placed horizontally in the centre of the card; in the re-engineered variant (shown above), it is placed vertically, on the right-hand edge of the card. (The two large chips next to it are the two gate arrays.)
The following versions of the 'early' variant exist:
- KDJ11-DA; 0.5MB, 15 MHz
- KDJ11-SA; BA200 box, 0.5MB, 15 MHz
- KDJ11-SB; BA200 box, 0.5MB, 18 MHz
The following are the versions of the 're-engineered' variant:
- KDJ11-DA (!); 0.5MB, 15 MHz
- KDJ11-DB; 1.5MB, 15 MHz
- KDJ11-SC; BA200 box, 1.5MB, 15 MHz
- KDJ11-SD; BA200 box, 1.5MB, 18 MHz
There .5MB/1.5MB versions are easy to tell apart visually: the .5MB cards have only two horizontal rows of DRAM chips in the large array on the left-hand side; on the 1.5MB cards, all six rows are present.
ROM Versions
The KDJ11-D supports the following ROMs:
| DEC Part Number | Version | Socket | Size | Application | Notes |
| 23-204E5-00 | 1.0 | E26 (High) | 16KB | PDP-11/53 | Supports only English and Spanish language options |
| 23-205E5-00 | 1.0 | E34 (Low) | 16KB | PDP-11/53 | Supports only English and Spanish language options |
| 23-261E5-00 | 2.0 | E26 (High) | 16KB | PDP-11/53 | Multi-language support, latest version |
| 23-262E5-00 | 2.0 | E34 (Low) | 16KB | PDP-11/53 | Multi-language support, latest version |
External links
- KDJ11-D/S CPU Module User's Guide (EK-KDJ1B-UG-002)
- KDJ11-D/S CPU System Maintenance (EK-246AA-MG-001)
