Difference between revisions of "DF10 Data Channel"

From Computer History Wiki
Jump to: navigation, search
m (link to new pages)
(Unredirect ITS.)
 
Line 22: Line 22:
 
* MIT modified DF10
 
* MIT modified DF10
  
Used on the [[Project MAC]] [[KA10]] DM and ML machines running [[ITS]].  The control word has the negated word count in bits 3-17, and the 21-bit memory address is split with bits 15-17 inverted in control bits 0-2, and bits 18-35 in the right half of the control word.
+
Used on the [[Project MAC]] [[KA10]] DM and ML machines running [[Incompatible Timesharing System|ITS]].  The control word has the negated word count in bits 3-17, and the 21-bit memory address is split with bits 15-17 inverted in control bits 0-2, and bits 18-35 in the right half of the control word.
  
 
{{semi-stub}}
 
{{semi-stub}}

Latest revision as of 06:32, 6 September 2023

The DF10 Data Channel is a channel for the early PDP-10 models (KA10 and KI10) which had the PDP-10 Memory Bus as a standard bus. It can connect to multi-port memory banks either directly, or via an MX10 Memory Data Multiplexor. It is also connected indirectly (through the device controllers which attach to it) to the system's I/O bus, to allow the CPU to control it.

It has limited capabilities, compared to most channels from other manufacturers: it supports only the following types of channel command words:

  • End of program
  • Jump to new CCW list
  • Discard data
  • Transfer data to/from memory

It is used with device controllers such as the RP10 disk controller‎, TM10 Magnetic Tape Control, and RH10 MASSBUS controller.

Models

  • DF10

Introduced 1968 for use with the KA10. Control words have a negated 18-bit word count in the left half, and an 18-bit memory address in the right half.

  • DF10-C

Introduced for use with the KI10. The memory address is expanded to 22 bits, and the control word is reduced to 14 bits.

  • MIT modified DF10

Used on the Project MAC KA10 DM and ML machines running ITS. The control word has the negated word count in bits 3-17, and the 21-bit memory address is split with bits 15-17 inverted in control bits 0-2, and bits 18-35 in the right half of the control word.

External links