Difference between revisions of "J-11 chip set"
From Computer History Wiki
(New page: 150px|thumb|right|J-11 A cpu for the PDP-11's... this one was a "single chip". {{stub}}) |
m (→External links: +J-11 Programmer's Reference) |
||
| (15 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
[[Image:J-11 cpu.jpg|150px|thumb|right|J-11]] | [[Image:J-11 cpu.jpg|150px|thumb|right|J-11]] | ||
| − | |||
| − | + | The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. | |
| + | |||
| + | It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an optional [[FPJ11 floating point accelerator]] [[integrated circuit|chip]] for higher performance. | ||
| + | |||
| + | Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]]. | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE] | ||
| + | * [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Programmers_Reference_Jan82.pdf J-11 Programmer's Reference] | ||
| + | * [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Control_Chip_Specification_Jun82.pdf J-11 Control Chip Specification] | ||
| + | * [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Data_Chip_Specification_Jul82.pdf J-11 Data Chip Specification] | ||
| + | * [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334 | ||
| + | * [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)] | ||
| + | ** [http://simh.trailing-edge.com/semi/ucode/j11/j11.mcr J-11 microcode] | ||
| + | |||
| + | [[Category: PDP-11 Processors]] | ||
Latest revision as of 22:19, 29 February 2024
The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, used in both the KDJ11 CPUs, and a variety of peripherals. It was implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.
It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating point support (using microcode), it can operate with an optional FPJ11 floating point accelerator chip for higher performance.
Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.
