Difference between revisions of "DJ11 Asynchronous 16-Line Multiplexer"

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Another group of jumpers allowed configuration of the input FIFO level at which an input interrupt occurred; choices were: 1, 5, 9, 17, or the sum of all selections (up to 32).
 
Another group of jumpers allowed configuration of the input FIFO level at which an input interrupt occurred; choices were: 1, 5, 9, 17, or the sum of all selections (up to 32).
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==Device registers==
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{| border=1
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! Register !! Abbreviation !! Address
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|-
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|Control and Status [[Register]]      || DJCSR || 760010
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|-
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|Receive Buffer Register              || DJRBUF || 760012
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|-
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|Transmit Control Register            || DJTCR || 760014
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|-
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|Transmit Buffer Register            || DJTBUF || 760016
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|-
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|Break Control and Status Register    || DJBCSR || 760014
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|}
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===760010: Control and Status Register (DJCSR)===
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{{16bit-header}}
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| TRDY || TIE || FFO || SEN || Unused || RWBR || Unused || MTSE || DONE || RIE || Unused || BCLR || MCLR || MAINT || HDSEL || REN
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{{16bit-bitout}}
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===760012: Receive Buffer Register (DJRBUF)===
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{{16bit-header}}
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| CHPR || ORUN || FRERR || PERR || colspan=4 style="text-align:center;" | Line || colspan=8 style="text-align:center;" | Received Char
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{{16bit-bitout}}
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===760014: Transmit Control Register (DJTCR)===
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{{16bit-header}}
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| colspan=16 | CHL15 <---> CHL00
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{{16bit-bitout}}
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===760016: Transmit Buffer Register (DJTBUF)===
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{{16bit-header}}
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| colspan=4 style="text-align:center;" | Unused || colspan=4 style="text-align:center;" | Line || colspan=8 style="text-align:center;" | Transmitted Char
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{{16bit-bitout}}
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===760014: Break Control and Status Register (DJBCSR)===
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{{16bit-header}}
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| colspan=16 | BKL15 <---> BKL00
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{{16bit-bitout}}
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To read/write the BCSR register, bit 10 of the CSR is set.
  
 
==Implementation==
 
==Implementation==

Revision as of 23:11, 23 September 2019

The DJ11 asynchronous serial line interface is a UNIBUS peripheral which provides up to 16 asynchronous serial lines. Both input and output used programmed I/O (with separate receive and transmit interrupts). On input, a 64-character FIFO buffer made over-runs unlikely. Modems were not supported.

It was less flexible than, and not as efficient as, the roughly contemporaneous DH11. It was effectively replaced by the DZ11, which was cheaper (it was a single hex board), and more flexible.

The DJ11 allowed support of either all 20mA or all EIA RS-232 serial lines, by means of a dual-width level converter board. The versions of the DJ11 were:

  • DJ11-AA - EIA level conversion
  • DJ11-AB - No level conversion (TTL levels)
  • DJ11-AC - EIA level conversion

The parameters for each line:

  • separate input and output baud rates (75 to 9600)
  • character length (5-8 bits)
  • stop bits (1, 1-1/2 and 2)
  • parity (odd, even, none)

could only be set with jumpers, in groups of four lines. A 'break' condition on the line (i.e. continuous assertion) could also be generated and detected.

Another group of jumpers allowed configuration of the input FIFO level at which an input interrupt occurred; choices were: 1, 5, 9, 17, or the sum of all selections (up to 32).

Device registers

Register Abbreviation Address
Control and Status Register DJCSR 760010
Receive Buffer Register DJRBUF 760012
Transmit Control Register DJTCR 760014
Transmit Buffer Register DJTBUF 760016
Break Control and Status Register DJBCSR 760014


760010: Control and Status Register (DJCSR)

TRDY TIE FFO SEN Unused RWBR Unused MTSE DONE RIE Unused BCLR MCLR MAINT HDSEL REN
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

760012: Receive Buffer Register (DJRBUF)

CHPR ORUN FRERR PERR Line Received Char
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

760014: Transmit Control Register (DJTCR)

CHL15 <---> CHL00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

760016: Transmit Buffer Register (DJTBUF)

Unused Line Transmitted Char
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

760014: Break Control and Status Register (DJBCSR)

BKL15 <---> BKL00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

To read/write the BCSR register, bit 10 of the CSR is set.

Implementation

The implementation took a single custom system unit backplane, containing multiple cards:

  • M7285 - Mux control (hex)
  • M7279 - Receive silo (dual)
  • M7280 (2) - Octal UARTs (quad)
  • M7821 - Interrupt control
  • M105 - Address selection

The -AA, -AB and -AC versions of the DJ11 also included one:

  • M5901 EIA conversion module
  • M5900 TTL 'conversion' module
  • M5902 20mA conversion module

respectively, which occupied a dual slot.

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Connector
Slot A B C D E F
1 UNIBUS In M105 M7821 M7279 Receive Silo
2 M7285 Mux Control
3     M7280 Octal UART
4 UNIBUS Out M7280 Octal UART

Distribution panels

The rack-mounted passive distribution panel used in the -AA EIA version was the H317-B distribution panel (the same as used by the DH11), which mounted directly into a standard 19" rack, and contained 16 DB-25P connectors. It was connected to the DJ11 with a pair of BC08S cables, which carried the 'main' signals (data, etc - i.e. non-modem control).

The -AC used an H317-A distribution panel, which had screw connectors.

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