Difference between revisions of "PDP-8/E"
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− | The '''PDP-8/E''' was an improved model in the [[PDP-8 family|PDP-8 line]], and introduced the [[OMNIBUS]] for interfacing to [[device controller]]s. | + | The '''PDP-8/E''' was an improved model in the [[PDP-8 family|PDP-8 line]] from [[Digital Equipment Corporation|DEC]], and introduced the [[OMNIBUS]] for interfacing to [[device controller]]s. |
The '''PDP-8/F''' was a cost-reduced version of the -8/E with the same [[Central Processing Unit|CPU]] and [[core memory|core]] [[main memory]], but only a single OMNIBUS [[backplane]]. The '''PDP-8/M''' is the [[Original Equipment Manufacturer|OEM]] version of the PDP-8/F. Both the /E and /M used the H9191-9216 20-slot [[DEC card form factor|quad]] OMNIBUS backplane. | The '''PDP-8/F''' was a cost-reduced version of the -8/E with the same [[Central Processing Unit|CPU]] and [[core memory|core]] [[main memory]], but only a single OMNIBUS [[backplane]]. The '''PDP-8/M''' is the [[Original Equipment Manufacturer|OEM]] version of the PDP-8/F. Both the /E and /M used the H9191-9216 20-slot [[DEC card form factor|quad]] OMNIBUS backplane. | ||
− | The -8/E's KK8-E [[Central Processing Unit|CPU]] consists of five [[DEC card form factor|quad]] boards (M8300 Major Registers, M8310 Register Control, M8320 Bus Loads, M8330 Timing Generator, M8560 [[Teletype]] Control); the MM8-E core memory that was standard on the -8/E consisted of sets of three quad boards (G227 X-Y Driver and Current Source, G104 Sense/Inhibit, H220 Memory Stack). | + | The -8/E-F-M's KK8-E [[Central Processing Unit|CPU]] consists of five [[DEC card form factor|quad]] boards (M8300 Major Registers, M8310 Register Control, M8320 Bus Loads, M8330 Timing Generator, M8560 [[Teletype]] Control); the MM8-E core memory that was standard on the -8/E consisted of sets of three quad boards (G227 X-Y Driver and Current Source, G104 Sense/Inhibit, H220 Memory Stack). |
Options included: | Options included: | ||
* KA8-E Positive I/O Bus Interface, to allow use of older PDP-8 devices | * KA8-E Positive I/O Bus Interface, to allow use of older PDP-8 devices | ||
− | * KM8-E | + | * KM8-E Memory Extension and Time-Share Option, which was needed to support more than 4K [[word]]s of memory, and allowed the computer to operate in either Executive Mode or User Mode (some sources refer to this as the 'MC8/E' - probably by analogy with earlier [[PDP-8 Memory Expansion units]] such as the MC8/I and MC8/L - but no DEC documentation refers to that name) |
* MP8-E Memory Parity | * MP8-E Memory Parity | ||
* KD8-E [[OMNIBUS|Data Break]] Interface | * KD8-E [[OMNIBUS|Data Break]] Interface | ||
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==External links== | ==External links== | ||
+ | * [http://www.bitsavers.org/pdf/dec/pdp8/pdp8e/ PDP-8/E documents] | ||
+ | ** [http://www.bitsavers.org/pdf/dec/pdp8/pdp8e/PDP-8E_IPB_Feb74.pdf PDP-8/E Illustrated Parts Breakdown] | ||
* [https://ethw.org/First-Hand:PDP-8/E_OMNIBUS_Ride First-Hand:PDP-8/E OMNIBUS Ride] - PDP-8/E Design Story | * [https://ethw.org/First-Hand:PDP-8/E_OMNIBUS_Ride First-Hand:PDP-8/E OMNIBUS Ride] - PDP-8/E Design Story | ||
* [https://hack42.nl/wiki/Digital_PDP-8f Digital PDP-8F] | * [https://hack42.nl/wiki/Digital_PDP-8f Digital PDP-8F] |
Revision as of 00:32, 19 September 2021
PDP-8/E | |
PDP-8/E front panel | |
Manufacturer: | DEC |
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Architecture: | PDP-8 |
Year Introduced: | 1970 |
Form Factor: | minicomputer |
Word Size: | 12 |
Logic Type: | TTL |
Design Type: | clocked random logic |
Clock Speed: | 385KHz |
Memory Speed: | 1.2 μseconds |
Physical Address Size: | 32KW (requires optional KM8-E) |
Virtual Address Size: | 4KW |
Memory Management: | bank selection, CPU mode |
Bus Architecture: | OMNIBUS |
Operating System: | OS/8, TSS/8 |
Predecessor(s): | PDP-8/I |
Successor(s): | PDP-8/A |
Price: | US$5K (CPU and 4KW memory) |
The PDP-8/E was an improved model in the PDP-8 line from DEC, and introduced the OMNIBUS for interfacing to device controllers.
The PDP-8/F was a cost-reduced version of the -8/E with the same CPU and core main memory, but only a single OMNIBUS backplane. The PDP-8/M is the OEM version of the PDP-8/F. Both the /E and /M used the H9191-9216 20-slot quad OMNIBUS backplane.
The -8/E-F-M's KK8-E CPU consists of five quad boards (M8300 Major Registers, M8310 Register Control, M8320 Bus Loads, M8330 Timing Generator, M8560 Teletype Control); the MM8-E core memory that was standard on the -8/E consisted of sets of three quad boards (G227 X-Y Driver and Current Source, G104 Sense/Inhibit, H220 Memory Stack).
Options included:
- KA8-E Positive I/O Bus Interface, to allow use of older PDP-8 devices
- KM8-E Memory Extension and Time-Share Option, which was needed to support more than 4K words of memory, and allowed the computer to operate in either Executive Mode or User Mode (some sources refer to this as the 'MC8/E' - probably by analogy with earlier PDP-8 Memory Expansion units such as the MC8/I and MC8/L - but no DEC documentation refers to that name)
- MP8-E Memory Parity
- KD8-E Data Break Interface
- KE8-E Extended Arithmetic Element (two quad boards), which supported hardware integer multiplication and division, one-bit double-word shifts, and normalization
- FPP12-P and FPP12-AP Floating Point Processor (24+12 bits)
- FPP12-AE Double Precision option (FPP12-AP only, 60+12 bits)
It could perform an addition to the accumulator in 2.6 μseconds, and a 12 by 12 bit multiplication with 24 bit result in 40 μseconds, using the math extension hardware.
The -8/M could be supplied with either a KC8-M Operator's Console, or a KC8-ML Programmer's Console, the latter being basically identical to the KC8-EA Programmer's Console of the basic -8/E.
Images
External links
- PDP-8/E documents
- First-Hand:PDP-8/E OMNIBUS Ride - PDP-8/E Design Story
- Digital PDP-8F
- PDP-8/M Restoration Project
v • d • e PDP-8 Computers, Software and Peripherals |
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PDP-8s: PDP-5 • PDP-8 • LINC-8 • PDP-8/S • PDP-8/I • PDP-8/L • PDP-12 • PDP-8/E • PDP-8/F • PDP-8/M • PDP-8/A
Workstations: VT78 Also: PDP-8 family • PDP-8 architecture • PDP-8 Memory Extension units |