Difference between revisions of "M-bus"
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Latest revision as of 13:10, 15 January 2024
The M-bus from DEC was a unique synchronous bus used in some VAXstations. It supported a 32-bit main memory address space, and 32-bit data transfers (although memory operations always transferred 4 longwords of data at a time).
Arbitration for use of the M-bus used a distributed LRU mechanism. The M-bus had considerable support for caches, including the capability to allow caches in CPUs connected to the M-bus to maintain consistent data. The M-bus also supported interrupts from peripherals to CPUs. It used parity for error detection.
